[coreboot-gerrit] Patch set updated for coreboot: southbridge/i82801gx: Fix sata AHCI for desktop models on ICH7

[Damien Zammit (damien@zamaudio.com)]

Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12923

-gerrit

commit bcab68db873b9a4af20ca2b330c1c31b7cd35dce
Author: Damien Zammit <damien at zamaudio.com>
Date:   Wed Jan 13 22:27:48 2016 +1100

    southbridge/i82801gx: Fix sata AHCI for desktop models on ICH7
    
    Tested on Intel D510MO
    Before this patch, I was unable to get the SATA controller into AHCI
    mode.  That is, I could never see PCI ID 8086:27c1 appearing on the bus.
    With sata_ahci set, controller now goes into AHCI mode and works. 8086:27c1
    
    Need to test this on a X60 with AHCI enabled to ensure no regressions with
    8086:27c5 (AHCI mode for mobile ich7)
    
    Change-Id: I4a3eabb5773106a0825fa2f30ee400fbfe636c7f
    Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
 src/southbridge/intel/i82801gx/sata.c | 53 ++++++++++++++++++++---------------
 1 file changed, 30 insertions(+), 23 deletions(-)

diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 29f878d..964d098 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2016 Damien Zammit <damien at zamaudio.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -26,6 +27,7 @@ static void sata_init(struct device *dev)
 {
 	u32 reg32;
 	u16 reg16;
+	u8 reg8;
 	u32 *ahci_bar;
 
 	/* Get the chip configuration */
@@ -39,6 +41,31 @@ static void sata_init(struct device *dev)
 	}
 
 	/* SATA configuration */
+	pci_write_config32(dev, 0x94,
+		pci_read_config32(dev, 0x94) | (1 << 23) | (3 << 7));
+
+	/* Enable clock gating for unused ports */
+	pci_write_config32(dev, 0x94,
+		pci_read_config32(dev, 0x94) | (1 << 26) | (1 << 27));
+
+	if (config->sata_ahci) {
+		/* Set map to ahci */
+		reg8 = pci_read_config8(dev, 0x90);
+		reg8 &= ~0xc3;
+		reg8 |= 0x40;
+		pci_write_config8(dev, 0x90, reg8);
+
+		/* Set subclass to ahci */
+		pci_write_config8(dev, 0x0a, 0x6);
+	} else {
+		/* Set map to ide */
+		reg8 = pci_read_config8(dev, 0x90);
+		reg8 &= ~0xc3;
+		pci_write_config8(dev, 0x90, reg8);
+
+		/* Set subclass to ide */
+		pci_write_config8(dev, 0x0a, 0x1);
+	}
 
 	/* Enable BARs */
 	pci_write_config16(dev, PCI_COMMAND, 0x0007);
@@ -86,34 +113,14 @@ static void sata_init(struct device *dev)
 		/* Interrupt Pin is set by D31IP.PIP */
 		pci_write_config8(dev, INTR_LN, 0x0a);
 
-		/* Set timings */
-		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
-				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
-				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
-		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
-				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
-
-		/* Sync DMA */
-		pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
-		pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
-
-		/* Set IDE I/O Configuration */
-		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
-		pci_write_config32(dev, IDE_CONFIG, reg32);
-
-		/* Set Sata Controller Mode. */
-		pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
-
 		/* In ACHI mode, bit[3:0] must always be set
 		 * (Port status is controlled through AHCI BAR)
 		 */
 		pci_write_config8(dev, 0x92, 0x0f);
 
 		ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
-		ahci_bar[3] = config->sata_ports_implemented;
+		ahci_bar[3] = config->sata_ports_implemented; // 00 01 10 11b
 
-		/* SATA Initialization register */
-		pci_write_config32(dev, 0x94, 0x1a000180);
 	} else {
 		printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
 		/* Set Sata Controller Mode. No Mapping(?) */
@@ -211,11 +218,11 @@ static struct device_operations sata_ops = {
 
 static const unsigned short sata_ids[] = {
 	0x27c0, /* Desktop Non-AHCI and Non-RAID Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
+	0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 	0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
+	0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
 	/* NOTE: Any of the below are not properly supported yet. */
-	0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 	0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
-	0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
 	0x27c6, /* ICH7M DH Raid Mode: 82801GHM (ICH7-M DH) */
 	0
 };