[coreboot-gerrit] New patch to review for coreboot: northbridge/intel/pineview: Native VGA init (CRT)
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Wed Jan 13 05:22:44 CET 2016
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12921
-gerrit
commit 2981f6f1bd38166cd93dc4b19bb8434e080ac137
Author: Damien Zammit <damien at zamaudio.com>
Date: Sun Jan 3 21:36:33 2016 +1100
northbridge/intel/pineview: Native VGA init (CRT)
VGA grub console works but display wobbles left/right
i915 driver reports: [drm:i915_irq_handler] *ERROR* pipe A underrun.
Monitor does not display 1920x1080 after modeset.
Other resolutions look out of sync
Cause: suspect single bug in raminit (chipset init)
Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/mainboard/intel/d510mo/Kconfig | 2 +
src/mainboard/intel/d510mo/acpi/platform.asl | 28 ++
src/mainboard/intel/d510mo/devicetree.cb | 13 +-
src/mainboard/intel/d510mo/dsdt.asl | 5 +-
src/mainboard/intel/d510mo/mainboard.c | 11 +-
src/mainboard/intel/d510mo/romstage.c | 1 +
src/northbridge/intel/pineview/Kconfig | 2 +
src/northbridge/intel/pineview/Makefile.inc | 1 +
src/northbridge/intel/pineview/acpi/pineview.asl | 2 +-
src/northbridge/intel/pineview/bootblock.c | 4 +-
src/northbridge/intel/pineview/early_init.c | 93 ++++--
src/northbridge/intel/pineview/gma.c | 380 +++++++++++++++++++++++
src/northbridge/intel/pineview/northbridge.c | 105 +++----
src/northbridge/intel/pineview/pineview.h | 5 +-
src/northbridge/intel/pineview/ram_calc.c | 3 -
src/northbridge/intel/pineview/raminit.c | 54 ++--
16 files changed, 584 insertions(+), 125 deletions(-)
diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig
index 7981f92..7184665 100644
--- a/src/mainboard/intel/d510mo/Kconfig
+++ b/src/mainboard/intel/d510mo/Kconfig
@@ -23,6 +23,8 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_WINBOND_W83627THG
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select INTEL_INT15
config MAX_CPUS
int
diff --git a/src/mainboard/intel/d510mo/acpi/platform.asl b/src/mainboard/intel/d510mo/acpi/platform.asl
new file mode 100644
index 0000000..6c92a4e
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi/platform.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice. */
+ Store(Arg0, PICM)
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) /* SMI Function */
+ Store (0, TRP0) /* Generate trap */
+ Return (SMIF) /* Return value of SMI handler */
+}
diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
index 221cc54..b2e4fbe 100644
--- a/src/mainboard/intel/d510mo/devicetree.cb
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -15,6 +15,8 @@
#
chip northbridge/intel/pineview # Northbridge
+ register "gfx.use_spread_spectrum_clock" = "0"
+
device cpu_cluster 0 on # APIC cluster
chip cpu/intel/socket_FCBGA559 # CPU
device lapic 0 on end # APIC
@@ -22,7 +24,10 @@ chip northbridge/intel/pineview # Northbridge
end
device domain 0 on # PCI domain
device pci 0.0 on end # Host Bridge
- device pci 2.0 off end # Integrated graphics controller
+ device pci 1.0 off end # PEG
+ device pci 2.0 on # Integrated graphics controller
+ subsystemid 0x8086 0x4f4d
+ end
chip southbridge/intel/i82801gx # Southbridge
register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0b"
@@ -36,9 +41,13 @@ chip northbridge/intel/pineview # Northbridge
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
+ register "gpe0_en" = "0x20000040"
device pci 1b.0 on end # Audio
- device pci 1c.0 on end # PCIe 1
+ device pci 1c.0 on # PCIe 1
+ device pci 0.0 on # NIC
+ end
+ end
device pci 1c.1 on end # PCIe 2
device pci 1c.2 on end # PCIe 3
device pci 1c.3 on end # PCIe 4
diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl
index c1f72f9..a7788bd 100644
--- a/src/mainboard/intel/d510mo/dsdt.asl
+++ b/src/mainboard/intel/d510mo/dsdt.asl
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -23,8 +23,11 @@ DefinitionBlock(
0x20090419 // OEM revision
)
{
+ #include "acpi/platform.asl"
#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
Scope (\_SB) {
Device (PCI0)
{
diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c
index 3b0ef0f..4f0f32b 100644
--- a/src/mainboard/intel/d510mo/mainboard.c
+++ b/src/mainboard/intel/d510mo/mainboard.c
@@ -16,19 +16,14 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <drivers/intel/gma/i915.h>
#include <pc80/mc146818rtc.h>
#include <device/pci.h>
-
-const struct i915_gpu_controller_info *
-intel_gma_get_controller_info(void)
-{
- return NULL;
-}
+#include <drivers/intel/gma/int15.h>
static void mainboard_enable(device_t dev)
{
- dev->ops->init = NULL;
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+ GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index b0bd0c0..6b4f0f6 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -50,6 +50,7 @@ static void mb_gpio_init(void)
outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
outl(0x000000fe, DEFAULT_GPIOBASE + 0x30);
outl(0x0000007e, DEFAULT_GPIOBASE + 0x34);
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 767bb81..c6bbee1 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -26,6 +26,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_DEBUG_RAM_SETUP
select LAPIC_MONOTONIC_TIMER
select LATE_CBMEM_INIT
+ select VGA
+ select INTEL_EDID
config BOOTBLOCK_NORTHBRIDGE_INIT
string
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
index f63018a..a4c08c8 100644
--- a/src/northbridge/intel/pineview/Makefile.inc
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -18,6 +18,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y)
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
+ramstage-y += gma.c
ramstage-y += acpi.c
romstage-y += ram_calc.c
diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl
index d32a906..dccbf49 100644
--- a/src/northbridge/intel/pineview/acpi/pineview.asl
+++ b/src/northbridge/intel/pineview/acpi/pineview.asl
@@ -33,7 +33,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
- Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
+ Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x10000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
index 1c04c28..06ffb43 100644
--- a/src/northbridge/intel/pineview/bootblock.c
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -1,8 +1,10 @@
#include <arch/io.h>
#define PCIEXBAR 0x60
+#define MMCONF_256_BUSES 16
+#define ENABLE 1
static void bootblock_northbridge_init(void)
{
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
- CONFIG_MMCONF_BASE_ADDRESS | 4 | 1);
+ CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSES | ENABLE);
}
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index dcbdbb1..9578a94 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -27,6 +27,13 @@
#define LPC PCI_DEV(0, 0x1f, 0)
#define D0F0 PCI_DEV(0, 0, 0)
+#define DPCGC 0xf6c
+#define GCFGC 0xc8c
+#define HPLLVCO 0xc38
+#define PCI_GCFC 0xf0
+#define CRCLK_PINEVIEW 0x02
+#define CDCLK_PINEVIEW 0x10
+
static void pineview_setup_bars(void)
{
u8 reg8;
@@ -66,35 +73,83 @@ static void pineview_setup_bars(void)
reg32 = MCHBAR32(0x30);
MCHBAR32(0x30) = 0x21800;
DMIBAR32(0x2c) = 0x86000040;
- pci_write_config8(D0F0, DEVEN, 0x09);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000);
reg8 = pci_read_config8(D0F0, 0xe5); // 0x10
- reg16 = pci_read_config16(PCI_DEV(0, 0x02, 0), 0x0); // 0x8086
+
+ pci_write_config8(D0F0, DEVEN, DEVEN_D2F0 | DEVEN_D0F0);
reg16 = pci_read_config16(D0F0, GGC);
- pci_write_config16(D0F0, GGC, 0x130);
- reg16 = pci_read_config16(D0F0, GGC);
- pci_write_config16(D0F0, GGC, 0x130);
- MCHBAR8(0xb08) = 0x20;
+ pci_write_config16(D0F0, GGC, 0x130); // 1MB GTT 8MB UMA
+
reg8 = pci_read_config8(D0F0, 0xe6); // 0x11
- reg16 = MCHBAR16(0xc8c);
- MCHBAR16(0xc8c) = reg16 | 0x0200;
- reg8 = MCHBAR8(0xc8c);
- MCHBAR8(0xc8c) = reg8;
- MCHBAR8(0xc8c) = 0x12;
- pci_write_config8(PCI_DEV(0, 0x02, 0), 0x62, 0x02);
- pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe8, 0x8000);
+
+ printk(BIOS_SPEW, "Set GFX clocks...");
+ reg16 = MCHBAR16(GCFGC);
+ MCHBAR16(GCFGC) = reg16 | (1 << 9);
+ reg16 &= ~0x7f;
+ reg16 |= CDCLK_PINEVIEW | CRCLK_PINEVIEW;
+ reg16 &= ~(1 << 9);
+ MCHBAR16(GCFGC) = reg16;
+
+ /* Graphics core */
+ reg8 = MCHBAR8(HPLLVCO);
+ reg8 &= 0x7;
+
+ reg16 = pci_read_config16(PCI_DEV(0,2,0), 0xcc) & ~0x1ff;
+
+ if (reg8 == 0x4) {
+ // 2666MHz
+ reg16 |= 0xad; //0xa7
+ } else if (reg8 == 0) {
+ // 3200MHz
+ reg16 |= 0xa0;
+ } else if (reg8 == 1) {
+ // 4000MHz
+ reg16 |= 0xad; //0xa7
+ }
+
+ pci_write_config16(PCI_DEV(0,2,0), 0xcc, reg16);
+
+ pci_write_config8(PCI_DEV(0,2,0), 0x62,
+ pci_read_config8(PCI_DEV(0,2,0), 0x62) & ~0x3);
+ pci_write_config8(PCI_DEV(0,2,0), 0x62,
+ pci_read_config8(PCI_DEV(0,2,0), 0x62) | 2);
+
+
+ /* LVDS from vendor bios */
MCHBAR32(0x3004) = 0x48000000;
MCHBAR32(0x3008) = 0xfffffe00;
- MCHBAR32(0xb08) = 0x06028220;
- MCHBAR32(0xff4) = 0xc6db8b5f;
- MCHBAR16(0xff8) = 0x024f;
- // PLL Voltage controlled oscillator
- //MCHBAR8(0xc38) = 0x04;
+ /* Enable LVDS */
+ //reg32 = MCHBAR32(0x3004);
+ //reg32 &= ~0xf1000000;
+ //reg32 |= 0x90000000;
+ //MCHBAR32(0x3004) = reg32;
+ //MCHBAR32(0x3008) = MCHBAR32(0x3008) | (1 << 9);
+
+ /* Enable VGA */
+ MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 15);
+
+ /* Disable LVDS */
+ MCHBAR32(0xb08) = MCHBAR32(0xb08) | (3 << 25);
+
+ MCHBAR32(0xff4) = 0x0c6db8b5f;
+ MCHBAR16(0xff8) = 0x24f;
+
+ MCHBAR32(0xb08) = MCHBAR32(0xb08) & 0xffffff00;
+ MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 5);
+
+ /* Hsync Vsync */
+ MCHBAR32(0xb68) = 0xbd000000;
+ MCHBAR32(0xb6c) = 0x000000bd;
+
+ /* Fix for GFX */
+ //pci_write_config16(PCI_DEV(0, 2, 0), 0xcc, 0x014d);
+ pci_write_config8(PCI_DEV(0, 2, 0), 0xf4, 0x4c);
+ //pci_write_config8(PCI_DEV(0, 2, 0), 0xf0, 0x12);
+ //pci_write_config32(PCI_DEV(0, 2, 0), 0xfc, 0xcef8a018);
- pci_write_config16(PCI_DEV(0, 0x02, 0), 0xcc, 0x014d);
reg32 = MCHBAR32(0x40);
MCHBAR32(0x40) = 0x0;
reg32 = MCHBAR32(0x40);
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
new file mode 100644
index 0000000..756a75e
--- /dev/null
+++ b/src/northbridge/intel/pineview/gma.c
@@ -0,0 +1,380 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Chromium OS Authors
+ * Copyright (C) 2013 Vladimir Serbinenko
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <kconfig.h>
+
+#include "drivers/intel/gma/i915_reg.h"
+#include "chip.h"
+#include "pineview.h"
+#include <drivers/intel/gma/intel_bios.h>
+#include <drivers/intel/gma/i915.h>
+#include <pc80/vga.h>
+#include <pc80/vga_io.h>
+
+#define GTTSIZE (1024*1024)
+#define GDRST 0xc0
+
+#define PGETBL2_CTL 0x20c4
+#define PGETBL2_1MB (1 << 8)
+
+#define PGETBL_CTL 0x2020
+#define PGETBL_1MB (3 << 1)
+#define PGETBL_512KB 0
+#define PGETBL_ENABLED 0x1
+
+#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
+ ADPA_CRT_HOTPLUG_WARMUP_10MS | \
+ ADPA_CRT_HOTPLUG_MONITOR_COLOR| \
+ ADPA_CRT_HOTPLUG_SAMPLE_4S | \
+ ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
+ ADPA_CRT_HOTPLUG_VOLREF_325MV | \
+ ADPA_CRT_HOTPLUG_ENABLE)
+
+static struct resource *gtt_res = NULL;
+static struct resource *mmio_res = NULL;
+
+#if 1
+static int gtt_setup(u8 *mmiobase)
+{
+ u32 gttbase;
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0,0));
+
+ gttbase = pci_read_config32(dev, BGSM);
+ printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase);
+
+ write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
+ udelay(50);
+ write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
+
+ write32(mmiobase + GFX_FLSH_CNTL, 0);
+
+ return 0;
+}
+#endif
+
+static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
+ struct device *vga, u8 *mmio, u8 *gtt, u32 physbase, u16 piobase)
+{
+ int i;
+ u32 hactive, vactive;
+ u32 temp;
+
+ printk(BIOS_SPEW, "gtt %x mmio %x addrport %x physbase %x\n", (u32)gtt, (u32)mmio, piobase, physbase);
+
+ printk(BIOS_DEBUG, "gma 1\n");
+
+ gtt_setup(mmio);
+
+ pci_write_config16(vga, 0x52, 0x130);
+
+ /* Disable VGA. */
+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
+
+ /* Disable pipes. */
+ write32(mmio + PIPECONF(0), 0);
+ write32(mmio + PIPECONF(1), 0);
+
+ write32(mmio + INSTPM, 0x800);
+
+ printk(BIOS_DEBUG, "gma 1b\n");
+
+
+// vga_io_init();
+
+// vga_misc_write(0x3);
+ vga_gr_write(0x18, 0);
+
+ printk(BIOS_DEBUG, "gma 1c\n");
+// vga_gr_write(0x6, vga_gr_read(0x6) & ~0xc);
+
+ printk(BIOS_DEBUG, "gma 2\n");
+
+ write32(mmio + VGA0, 0x200074);
+ write32(mmio + VGA1, 0x200074);
+
+ write32(mmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN);
+ write32(mmio + DSPCLK_GATE_D, 0);
+ write32(mmio + FW_BLC, 0x03060106);
+ write32(mmio + FW_BLC2, 0x00000306);
+
+ write32(mmio + ADPA, ADPA_DAC_ENABLE
+ | ADPA_PIPE_A_SELECT
+ | ADPA_HOTPLUG_BITS
+ | ADPA_USE_VGA_HVPOLARITY
+ | ADPA_VSYNC_CNTL_ENABLE
+ | ADPA_HSYNC_CNTL_ENABLE
+ | ADPA_DPMS_ON
+ );
+
+ write32(mmio + 0x7041c, 0x0);
+
+ write32(mmio + DPLL_MD(0), 0x3);
+ write32(mmio + DPLL_MD(1), 0x3);
+ write32(mmio + DSPCNTR(1), 0x1000000);
+ write32(mmio + PIPESRC(1), 0x027f01df);
+
+
+ printk(BIOS_DEBUG, "gma 3\n");
+
+ vga_misc_write(0x67);
+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
+ 0xff
+ };
+ vga_cr_write(0x11, 0);
+
+ for (i = 0; i <= 0x18; i++)
+ vga_cr_write(i, cr[i]);
+
+ // Disable screen memory to prevent garbage from appearing.
+ vga_sr_write(1, vga_sr_read(1) | 0x20);
+ printk(BIOS_DEBUG, "gma 4\n");
+ hactive = 640;
+ vactive = 400;
+
+ printk(BIOS_DEBUG, "gma 5\n");
+ mdelay(1);
+ write32(mmio + DPLL(0),
+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
+ | DPLL_VGA_MODE_DIS
+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
+ | 0x400601
+ );
+ mdelay(1);
+ write32(mmio + DPLL(0),
+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
+ | DPLL_VGA_MODE_DIS
+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
+ | 0x400601
+ );
+
+ write32(mmio + ADPA, ADPA_DAC_ENABLE
+ | ADPA_PIPE_A_SELECT
+ | ADPA_HOTPLUG_BITS
+ | ADPA_USE_VGA_HVPOLARITY
+ | ADPA_VSYNC_CNTL_ENABLE
+ | ADPA_HSYNC_CNTL_ENABLE
+ | ADPA_DPMS_ON
+ );
+
+ write32(mmio + HTOTAL(1), 0x031f027f);
+ write32(mmio + HBLANK(1), 0x03170287);
+ write32(mmio + HSYNC(1), 0x02ef028f);
+ write32(mmio + VTOTAL(1), 0x020c01df);
+ write32(mmio + VBLANK(1), 0x020401e7);
+ write32(mmio + VSYNC(1), 0x01eb01e9);
+
+ write32(mmio + HTOTAL(0),
+ ((hactive - 1) << 16)
+ | (hactive - 1));
+ write32(mmio + HBLANK(0),
+ ((hactive - 1) << 16)
+ | (hactive - 1));
+ write32(mmio + HSYNC(0),
+ ((hactive - 1) << 16)
+ | (hactive - 1));
+
+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16)
+ | (vactive - 1));
+ write32(mmio + VBLANK(0), ((vactive - 1) << 16)
+ | (vactive - 1));
+ write32(mmio + VSYNC(0),
+ ((vactive - 1) << 16)
+ | (vactive - 1));
+
+ printk(BIOS_DEBUG, "gma 6\n");
+ write32(mmio + PF_WIN_POS(0), 0);
+
+ write32(mmio + PIPESRC(0), (639 << 16) | 399);
+ write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+ write32(mmio + PFIT_CONTROL, 0x0);
+
+ mdelay(1);
+
+ write32(mmio + FDI_RX_CTL(0), 0x00002040);
+ mdelay(1);
+ write32(mmio + FDI_RX_CTL(0), 0x80002050);
+ write32(mmio + FDI_TX_CTL(0), 0x00044000);
+ mdelay(1);
+ write32(mmio + FDI_TX_CTL(0), 0x80044000);
+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+
+ write32(mmio + VGACNTRL, 0x0);
+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+ mdelay(1);
+
+ printk(BIOS_DEBUG, "gma 7\n");
+ write32(mmio + ADPA, ADPA_DAC_ENABLE
+ | ADPA_PIPE_A_SELECT
+ | ADPA_HOTPLUG_BITS
+ | ADPA_USE_VGA_HVPOLARITY
+ | ADPA_VSYNC_CNTL_ENABLE
+ | ADPA_HSYNC_CNTL_ENABLE
+ | ADPA_DPMS_ON
+ );
+
+ write32(mmio + DSPFW3, 0x7f3f00c1);
+ write32(mmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
+ write32(mmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5));
+ write32(mmio + CACHE_MODE_1, 0x380 & ~(1 << 9));
+
+ printk(BIOS_DEBUG, "gma 8\n");
+
+ for (i = 0; i < (8192 - 512) / 4; i++) {
+ outl((i << 2) | 1, piobase);
+ outl(physbase + (i << 12) + 1, piobase + 4);
+ }
+
+ temp = read32(mmio + PGETBL_CTL);
+ printk(BIOS_INFO, "GTT PGETBL_CTL register : 0x%08x\n", temp);
+ temp = read32(mmio + PGETBL2_CTL);
+ printk(BIOS_INFO, "GTT PGETBL2_CTL register: 0x%08x\n", temp);
+
+ /* Clear interrupts. */
+ write32(mmio + DEIIR, 0xffffffff);
+ write32(mmio + SDEIIR, 0xffffffff);
+ write32(mmio + IIR, 0xffffffff);
+ write32(mmio + IMR, 0xffffffff);
+ write32(mmio + EIR, 0xffffffff);
+
+ vga_textmode_init();
+
+ /* Enable screen memory. */
+ vga_sr_write(1, vga_sr_read(1) & ~0x20);
+}
+
+static void gma_func0_init(struct device *dev)
+{
+ u32 reg32;
+
+ ///* Unconditionally reset graphics */
+ //printk(BIOS_SPEW, "Reset GFX...");
+ //pci_write_config8(dev, GDRST, 1);
+ //udelay(50);
+ //pci_write_config8(dev, GDRST, 0);
+ ///* wait for device to finish */
+ //while (pci_read_config8(dev, GDRST) & 1) { };
+ //printk(BIOS_SPEW, "done\n");
+
+ /* IGD needs to be Bus Master */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* Find base addresses */
+ mmio_res = find_resource(dev, 0x10);
+ gtt_res = find_resource(dev, 0x1c);
+
+ struct northbridge_intel_pineview_config *conf = dev->chip_info;
+
+ if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
+ /* PCI Init, will run VBIOS */
+ pci_dev_init(dev);
+ } else {
+ u32 physbase;
+ struct resource *pio_res;
+
+ pio_res = find_resource(dev, 0x14);
+
+ physbase = pci_read_config32(dev, 0x5c) & ~0xf;
+
+ if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) {
+ printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n",
+ mmio_res->base);
+ intel_gma_init(conf, dev, res2mmio(mmio_res, 0, 0),
+ res2mmio(gtt_res, 0, 0),
+ physbase, pio_res->base);
+ }
+
+ /* Linux relies on VBT for panel info. */
+ generate_fake_intel_oprom(&conf->gfx, dev,
+ "$VBT PINEVIEW ");
+ }
+}
+
+static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor &
+ 0xffff));
+ }
+}
+
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+ if (!dev) {
+ return NULL;
+ }
+ struct northbridge_intel_pineview_config *chip = dev->chip_info;
+ return &chip->gfx;
+}
+
+#if 0
+static void gma_ssdt(device_t device)
+{
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+ if (!gfx) {
+ return;
+ }
+
+ drivers_intel_gma_displays_ssdt_generate(gfx);
+}
+#endif
+
+static struct pci_operations gma_pci_ops = {
+ .set_subsystem = gma_set_subsystem,
+};
+
+static struct device_operations gma_func0_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .acpi_fill_ssdt_generator = 0, //gma_ssdt,
+ .init = gma_func0_init,
+ .scan_bus = 0,
+ .enable = 0,
+ .ops_pci = &gma_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] =
+{
+ 0xa001, 0
+};
+
+static const struct pci_driver gma __pci_driver = {
+ .ops = &gma_func0_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 21f133d..469a4ad 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -29,42 +29,58 @@
#include <cbmem.h>
#include <northbridge/intel/pineview/pineview.h>
-/* Reserve segments A and B:
+/* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
+ * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
*/
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 128;
+static void add_fixed_resources(device_t dev, int index)
+{
+ struct resource *resource;
+
+ resource = new_resource(dev, index++);
+ resource->base = (resource_t) 0xfed00000;
+ resource->size = (resource_t) 0x00100000;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ mmio_resource(dev, index++, legacy_hole_base_k,
+ (0xc0000 >> 10) - legacy_hole_base_k);
+ reserved_ram_resource(dev, index++, 0xc0000 >> 10,
+ (0x100000 - 0xc0000) >> 10);
+}
+
static void mch_domain_read_resources(device_t dev)
{
u64 tom, touud;
- u32 tomk, tolud, uma_sizek = 0, usable_tomk;
+ u32 tomk, tolud;
u32 pcie_config_base, pcie_config_size;
pci_domain_read_resources(dev);
/* Top of Upper Usable DRAM, including remap */
- touud = pci_read_config16(dev, 0xa2);
+ touud = pci_read_config16(dev, TOUUD);
touud <<= 20;
/* Top of Lower Usable DRAM */
- tolud = pci_read_config16(dev, 0xb0) & 0xfff0;
+ tolud = pci_read_config16(dev, TOLUD) & 0xfff0;
tolud <<= 16;
/* Top of Memory - does not account for any UMA */
- tom = pci_read_config16(dev, 0xa0) & 0x1ff;
+ tom = pci_read_config16(dev, TOM) & 0x1ff;
tom <<= 27;
- printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
+ printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ",
touud, tolud, tom);
tomk = tolud >> 10;
- /* Graphics memory comes next */
- const u16 ggc = pci_read_config16(dev, GGC);
-
/* Graphics memory */
+ const u16 ggc = pci_read_config16(dev, GGC);
const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);
tomk -= gms_sizek;
@@ -74,45 +90,40 @@ static void mch_domain_read_resources(device_t dev)
printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
tomk -= gsm_sizek;
- uma_sizek = gms_sizek + gsm_sizek;
+ //const u32 tseg_basek = pci_read_config32(dev, TSEG) >> 10;
+ //tomk -= 1024;
- usable_tomk = ALIGN_DOWN(tomk, 64 << 10);
- if (tomk - usable_tomk > (16 << 10))
- usable_tomk = tomk;
-
- printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10);
+ const u32 igd_basek = pci_read_config32(dev, GBSM) >> 10;
+ const u32 gtt_basek = pci_read_config32(dev, BGSM) >> 10;
/* Report the memory regions */
- ram_resource(dev, 3, 0, legacy_hole_base_k);
- ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
- (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k)));
+ ram_resource(dev, 3, 0, 640);
+ ram_resource(dev, 4, 768, tomk - 768);
+ //reserved_ram_resource(dev, 5, tseg_basek, 1024);
- mmio_resource(dev, 5, legacy_hole_base_k,
- (0xc0000 >> 10) - legacy_hole_base_k);
+ reserved_ram_resource(dev, 6, gtt_basek, gsm_sizek);
+ reserved_ram_resource(dev, 7, igd_basek, gms_sizek);
/*
- * If >= 4GB installed then memory from TOLUD to 4GB
+ * If > 4GB installed then memory from TOLUD to 4GB
* is remapped above TOM, TOUUD will account for both
*/
touud >>= 10; /* Convert to KB */
if (touud > 4096 * 1024) {
- ram_resource(dev, 6, 4096 * 1024, touud - (4096 * 1024));
+ ram_resource(dev, 8, 4096 * 1024, touud - (4096 * 1024));
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
(touud >> 10) - 4096);
}
- printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
- "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10);
- /* Don't use uma_resource() as our UMA touches the PCI hole. */
- fixed_mem_resource(dev, 7, tomk, uma_sizek, IORESOURCE_RESERVE);
-
if (decode_pciebar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
- "size=0x%x\n", pcie_config_base, pcie_config_size);
- fixed_mem_resource(dev, 8, pcie_config_base >> 10,
+ "size=0x%x\n", pcie_config_base, pcie_config_size);
+ fixed_mem_resource(dev, 9, pcie_config_base >> 10,
pcie_config_size >> 10, IORESOURCE_RESERVE);
}
+ add_fixed_resources(dev, 10);
+
set_top_of_ram(tomk << 10);
}
@@ -121,7 +132,7 @@ static void mch_domain_set_resources(device_t dev)
struct resource *resource;
int i;
- for (i = 3; i < 9; ++i) {
+ for (i = 3; i < 13; ++i) {
/* Report read resources. */
resource = probe_resource(dev, i);
if (resource)
@@ -190,41 +201,7 @@ static void enable_dev(device_t dev)
}
}
-static void pineview_init(void *const chip_info)
-{
- int dev, fn;
-
- struct device *const d0f0 = dev_find_slot(0, 0);
-
- const struct {
- u8 fn;
- u8 bitbase;
- } intfunc[] = {
- {0, 0},
- {0, 1}, /* PEG */
- {1, 3}, /* IGD */
- {3, 6}, /* ME */
- };
-
- /* Hide internal functions based on devicetree info. */
- for (dev = 3; dev > 0; --dev) {
- for (fn = intfunc[dev].fn; fn >= 0; --fn) {
- const struct device *const d =
- dev_find_slot(0, PCI_DEVFN(dev, fn));
- if (!d || d->enabled) continue;
- const u32 deven = pci_read_config32(d0f0, DEVEN);
- pci_write_config32(d0f0, DEVEN, deven
- & ~(1 << (intfunc[dev].bitbase + fn)));
- }
- }
-
- const u32 deven = pci_read_config32(d0f0, DEVEN);
- if (!(deven & (0xf << 6)))
- pci_write_config32(d0f0, DEVEN, deven & ~(1 << 14));
-}
-
struct chip_operations northbridge_intel_pineview_ops = {
CHIP_NAME("Intel Pineview Northbridge")
.enable_dev = enable_dev,
- .init = pineview_init,
};
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index d807340..83752ce 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -47,8 +47,8 @@
#define DEVEN_D2F1 (1 << 4)
#ifndef BOARD_DEVEN
-#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
-#endif /* BOARD_DEVEN */
+#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 )
+#endif
#define PAM0 0x90
#define PAM1 0x91
@@ -92,7 +92,6 @@
#define GMADR 0x18
#define GTTADR 0x1c
#define BSM 0x5c
-#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */
#define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x))
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index c273071..af1ca72 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -42,9 +42,6 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
{0, 0},
};
- if (!dev)
- return 0;
-
pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
// MMCFG not supported or not enabled.
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index a80aeac..4ff8c3f 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -35,6 +35,7 @@
#define PRINTK_DEBUG(x...)
#endif
+
#define MAX_TCLK_667 0x30
#define MAX_TCLK_800 0x25
#define MAX_TAC_667 0x45
@@ -2057,11 +2058,12 @@ static void sdram_mmap_regs(struct sysinfo *s)
reclaimbase = 0;
reclaimlimit = 0;
ggc = pci_read_config16(PCI_DEV(0,0,0), GGC);
+ printk(BIOS_DEBUG, "GGC = 0x%04x\n", ggc);
gfxsize = ggc_to_uma[(ggc & 0xf0) >> 4];
- gttsize = ggc_to_gtt[(ggc & 0xc00) >> 8];
+ gttsize = ggc_to_gtt[(ggc & 0x300) >> 8];
tom = s->channel_capacity[0];
- tsegsize = 0x1; // 1MB
+ tsegsize = 0x0; // 0MB
mmiosize = 0x400; // 1GB
reclaim = false;
@@ -2085,16 +2087,21 @@ static void sdram_mmap_regs(struct sysinfo *s)
tsegbase = gttbase - tsegsize;
/* Program the regs */
- pci_write_config16(PCI_DEV(0,0,0), 0xb0, (u16)(tolud << 4));
- pci_write_config16(PCI_DEV(0,0,0), 0xa0, (u16)(tom >> 6));
+ pci_write_config16(PCI_DEV(0,0,0), TOLUD, (u16)(tolud << 4));
+ pci_write_config16(PCI_DEV(0,0,0), TOM, (u16)(tom >> 6));
if (reclaim) {
pci_write_config16(PCI_DEV(0,0,0), 0x98, (u16)(reclaimbase >> 6));
pci_write_config16(PCI_DEV(0,0,0), 0x9a, (u16)(reclaimlimit >> 6));
}
- pci_write_config16(PCI_DEV(0,0,0), 0xa2, (u16)(touud));
- pci_write_config32(PCI_DEV(0,0,0), 0xa4, gfxbase << 20);
- pci_write_config32(PCI_DEV(0,0,0), 0xa8, gttbase << 20);
- pci_write_config32(PCI_DEV(0,0,0), 0xac, tsegbase << 20);
+ pci_write_config16(PCI_DEV(0,0,0), TOUUD, (u16)(touud));
+ pci_write_config32(PCI_DEV(0,0,0), GBSM, gfxbase << 20);
+ pci_write_config32(PCI_DEV(0,0,0), BGSM, gttbase << 20);
+ pci_write_config32(PCI_DEV(0,0,0), TSEG, tsegbase << 20);
+
+ printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n",
+ pci_read_config32(PCI_DEV(0,0,0), GBSM), gfxbase << 20);
+ printk(BIOS_DEBUG, "BGSM (gtt) = verified %08x (written %08x)\n",
+ pci_read_config32(PCI_DEV(0,0,0), BGSM), gttbase << 20);
}
static void sdram_enhancedmode(struct sysinfo *s)
@@ -2189,7 +2196,7 @@ static void sdram_enhancedmode(struct sysinfo *s)
MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0xc0000) | 0x40000;
u32 clkcx[2][2][3] = {
{
- {0, 0x0c080302, 0x08010204}, // 667
+ {0, 0x04080102, 0x08010204}, // 667
{0x02040000, 0x08100102, 0}
},
{
@@ -2329,14 +2336,16 @@ static void sdram_powersettings(struct sysinfo *s)
MCHBAR8(0xff8+3) = MCHBAR8(0xff8+3) & ~0x80;
MCHBAR16(0xff0) = MCHBAR16(0xff0) & ~0x1fff;
MCHBAR32(0xfb0) = MCHBAR32(0xfb0) & ~0x0001ffff;
- MCHBAR16(0x48) = (MCHBAR16(0x48) & ~0x03ff) & 0x6;
- MCHBAR32(0x20) = (MCHBAR32(0x20) & ~0xffffffff) | 0x20;
+ MCHBAR16(0x48) = (MCHBAR16(0x48) & ~0x03ff) | 0x6;
+ MCHBAR32(0x20) = 0x20;
+
MCHBAR8(0xd14) = MCHBAR8(0xd14) & ~1;
MCHBAR8(0x239) = s->selected_timings.CAS - 1 + 0x15;
- MCHBAR16(0x2d1) = (MCHBAR16(0x2d1) & ~0x07fc) | 0x40;
+ MCHBAR16(0x2d1) = (MCHBAR16(0x2d1) & ~0x03fc) | 0x40; // CG1
MCHBAR16(0x6d1) = (MCHBAR16(0x6d1) & ~0x0fff) | 0xd00;
- MCHBAR16(0x210) = MCHBAR16(0x210) & ~0x0d80;
- MCHBAR16(0xf6c+2) = 0xffff;
+ //MCHBAR16(0x6d1) = (MCHBAR16(0x6d1) & ~0x05ff) | 0x100; // CG2
+ MCHBAR16(0x210) = MCHBAR16(0x210) & ~0x0d80; // CG3
+ MCHBAR16(0xf6c+2) = 0x0000;
/* Sequencing */
MCHBAR32(0x14) = (MCHBAR32(0x14) & ~0x1fffffff) | 0x1f643fff;
@@ -2346,14 +2355,11 @@ static void sdram_powersettings(struct sysinfo *s)
/* Power */
MCHBAR32(0x1104) = (MCHBAR32(0x1104) & ~0xffff0003) | 0x10100000;
MCHBAR32(0x1108) = (MCHBAR32(0x1108) & ~0x0001bff7) | 0x00000078;
- if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) {
- MCHBAR16(0x110c) = (MCHBAR16(0x110c) & ~0x03ff) | 0xc8;
- } else {
- MCHBAR16(0x110c) = (MCHBAR16(0x110c) & ~0x03ff) | 0x100;
- }
+ MCHBAR16(0x110c) = (MCHBAR16(0x110c) & ~0x03ff);
+
j = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 0 : 1;
- MCHBAR32(0x1110) = (MCHBAR32(0x1110) & ~0x1fff37f) | 0x10810700;
+ MCHBAR32(0x1110) = (MCHBAR32(0x1110) & ~0x1fff37f) | 0x10810500;
MCHBAR8(0x1114) = (MCHBAR8(0x1114) & ~0x07) | 1;
MCHBAR8(0x1124) = MCHBAR8(0x1124) & ~0x02;
@@ -2384,7 +2390,7 @@ static void sdram_powersettings(struct sysinfo *s)
}
MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0x0f000000) | 0x20000000 | reg32;
MCHBAR32(0x2d1) = (MCHBAR32(0x2d1) & ~0x00f00000) | 0x00f00000;
- MCHBAR32(0x6d0) = (MCHBAR32(0x6d0) & ~0x001ff000) | (0xbf << 20);
+ MCHBAR32(0x6d0) = (MCHBAR32(0x6d0) & ~0x1ff00000) | (0xbf << 20);
MCHBAR16(0x610) = (MCHBAR16(0x610) & ~0x1f7f) | (0xb << 8) | (7 << 4) | 0xb;
MCHBAR16(0x612) = 0x3264;
MCHBAR16(0x614) = (MCHBAR16(0x614) & ~0x3f3f) | (0x14 << 8) | 0xa;
@@ -2395,7 +2401,7 @@ static void sdram_powersettings(struct sysinfo *s)
static void sdram_programddr(void)
{
MCHBAR16(0x6d1) = (MCHBAR16(0x6d1) & ~0x03ff) | 0x100;
- MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0x003f) | 0x10;
+ MCHBAR8(0x210) = (MCHBAR8(0x210) & ~0x3f) | 0x10;
MCHBAR16(0x2d1) = (MCHBAR16(0x2d1) & ~0x7000) | 0x2000;
MCHBAR8(0x180) = MCHBAR8(0x180) & ~0xe;
MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0xc;
@@ -2468,7 +2474,7 @@ static void sdram_programdqdqs(struct sysinfo *s)
repeat = 2;
feature = 0;
cwb = 0;
- pimdclk = 0;
+ pimdclk = 3;
reg32 = 0;
push = 0;
reg8 = 0;
@@ -2639,6 +2645,8 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
sdram_periodic_rcomp();
PRINTK_DEBUG("Done periodic RCOMP\n");
+ MCHBAR32(0xfd0) = 0x001b0204;
+
/* Set init done */
MCHBAR32(0x268) = MCHBAR32(0x268) | 0x40000000;
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