[coreboot-gerrit] Patch set updated for coreboot: Braswell: Fix P-state table

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12731

-gerrit

commit b8f813aae26ef8398b9f1f11646c582cc1c769af
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Wed Aug 5 17:01:55 2015 +0530

    Braswell: Fix P-state table
    
    Incorrect bus-core-ratio been used to generate P-state table
    
    Original-Reviewed-on: https://chromium-review.googlesource.com/290681
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    
    Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 src/soc/intel/braswell/include/soc/msr.h |  3 ++-
 src/soc/intel/braswell/ramstage.c        |  2 +-
 src/soc/intel/braswell/tsc_freq.c        | 27 ++++++++++++++++++++++++---
 3 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h
index 93701aa..99ad06c 100644
--- a/src/soc/intel/braswell/include/soc/msr.h
+++ b/src/soc/intel/braswell/include/soc/msr.h
@@ -43,6 +43,7 @@
 #define MSR_CPU_THERM_CFG2		0x674
 #define MSR_CPU_THERM_SENS_CFG		0x675
 
-#define BUS_FREQ_KHZ			100000	/* 100 MHz */
+/* Read BCLK from MSR */
+unsigned bus_freq_khz(void);
 
 #endif /* _SOC_MSR_H_ */
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 749feaf..5f163e4 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -128,7 +128,7 @@ static void fill_in_pattrs(void)
 	attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */
 
 	/* Set bus clock speed */
-	attrs->bclk_khz = BUS_FREQ_KHZ;
+	attrs->bclk_khz = bus_freq_khz();
 }
 
 static inline void set_acpi_sleep_type(int val)
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c
index 284ba2b..afd36ad 100644
--- a/src/soc/intel/braswell/tsc_freq.c
+++ b/src/soc/intel/braswell/tsc_freq.c
@@ -26,12 +26,33 @@
 #endif
 #include <stdint.h>
 
+unsigned bus_freq_khz(void)
+{
+	msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
+	switch (clk_info.lo & 0xF) {
+	case 0: return 83333;
+	case 1: return 100000;
+	case 2: return 133333;
+	case 3: return 116666;
+	case 4: return 80000;
+	case 5: return 93333;
+	case 6: return 90000;
+	case 7: return 88900;
+	case 8: return 87500;
+	default: return 0;
+	}
+}
+
 unsigned long tsc_freq_mhz(void)
 {
-	msr_t ia_core_ratios;
+	msr_t platform_info;
+	unsigned bclk_khz = bus_freq_khz();
+
+	if (!bclk_khz)
+		return 0;
 
-	ia_core_ratios = rdmsr(MSR_IACORE_RATIOS);
-	return (BUS_FREQ_KHZ * ((ia_core_ratios.lo >> 16) & 0x3f)) / 1000;
+	platform_info = rdmsr(MSR_PLATFORM_INFO);
+	return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
 }
 
 #if !ENV_SMM