[coreboot-gerrit] Patch set updated for coreboot: Strago: Enable native mode on sd card cd line

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12741

-gerrit

commit d3db1563f6f578c2cfe577549044d16a9ac66ba8
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Date:   Wed Nov 4 14:25:15 2015 -0800

    Strago: Enable native mode on sd card cd line
    
    Configuring Native Mode enables the card present bit in
    sd card controller register.
    
    TEST=Sd Card Plug/Unplug should work in OS and DepthCharge.
    
    Original-Reviewed-on: https://chromium-review.googlesource.com/310847
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    
    Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5
    Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
    Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
 src/mainboard/intel/strago/gpio.c         | 2 +-
 src/soc/intel/braswell/include/soc/gpio.h | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c
old mode 100755
new mode 100644
index 8b6a0e7..b686853
--- a/src/mainboard/intel/strago/gpio.c
+++ b/src/mainboard/intel/strago/gpio.c
@@ -74,7 +74,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	Native_M1, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
 	Native_M1, /* 80  USB_OC0_B */
-	NATIVE_INT(1, L1), /* 81  SDMMC3_CD_B */
+	NATIVE_INT_PU20K(1, L1), /* 81  SDMMC3_CD_B */
 	GPIO_NC,  /* 82  spkr	 asummed gpio number */
 	Native_M1, /* 83 SUSPWRDNACK */
 	SPARE_PIN,/* 84 spare pin */
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index 08cfd0c..5c1d7d2 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -274,6 +274,11 @@
 		   | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\
 	.pad_conf1 = PAD_CONFIG1_DEFAULT0 }
 
+#define NATIVE_INT_PU20K(mode, int_sel) {\
+	.pad_conf0 = PAD_PULL_UP_20K | PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \
+		   | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\
+	.pad_conf1 = PAD_CONFIG1_DEFAULT0 }
+
 #define SPEAKER \
 {	.pad_conf0 = PAD_CONFIG0_DEFAULT0, \
 	.pad_conf1 = PAD_CONFIG1_DEFAULT0 }