[coreboot-gerrit] Patch set updated for coreboot: cpu/qemu-x86/romstage_entry.inc: Remove redunant cache-as-ram code

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12878

-gerrit

commit a7d67ca96799273a0cf89b990bd0703971799fee
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Fri Jan 8 22:51:21 2016 -0800

    cpu/qemu-x86/romstage_entry.inc: Remove redunant cache-as-ram code
    
    This CPU doesn't use cache-as-ram; however, since it uses a C
    environment bootblock, any such setup would have to be handled in the
    bootblock anyway.
    Ramstage is succesfully loaded and executed with this change.
    
    Change-Id: Ib9a70fed933ac484f8a5632b6b8f1ab9f69a9ae0
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/qemu-x86/romstage.h                    | 18 ++++++++++++++++++
 src/cpu/qemu-x86/romstage_entry.inc            | 24 ++++--------------------
 src/mainboard/emulation/qemu-i440fx/romstage.c |  4 ++--
 src/mainboard/emulation/qemu-q35/romstage.c    |  4 ++--
 4 files changed, 26 insertions(+), 24 deletions(-)

diff --git a/src/cpu/qemu-x86/romstage.h b/src/cpu/qemu-x86/romstage.h
new file mode 100644
index 0000000..ea628c8
--- /dev/null
+++ b/src/cpu/qemu-x86/romstage.h
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _CPU_QEMU_X86_ROMSTAGE_H_
+#define _CPU_QEMU_X86_ROMSTAGE_H_
+
+/* romstage C entry point */
+void main(void);
+
+#endif	/* _CPU_QEMU_X86_ROMSTAGE_H_ */
diff --git a/src/cpu/qemu-x86/romstage_entry.inc b/src/cpu/qemu-x86/romstage_entry.inc
index fcd2d3b..2c900f9 100644
--- a/src/cpu/qemu-x86/romstage_entry.inc
+++ b/src/cpu/qemu-x86/romstage_entry.inc
@@ -19,34 +19,18 @@
 #include <cpu/x86/post_code.h>
 #include <cbmem.h>
 
-#define CACHE_AS_RAM_SIZE 0x10000
-#define CACHE_AS_RAM_BASE 0xd0000
+#define STACK_SIZE 0x10000
+#define STACK_BASE 0xd0000
 
 #define CPU_PHYSMASK_HI  (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
-
-cache_as_ram:
+qemu_x86_assembly_entry:
 	post_code(0x20)
-       /* Clear the cache memory region. This will also fill up the cache */
-	movl	$CACHE_AS_RAM_BASE, %esi
-	movl	%esi, %edi
-	movl	$(CACHE_AS_RAM_SIZE >> 2), %ecx
-	// movl	$0x23322332, %eax
-	xorl	%eax, %eax
-	rep	stosl
 
-	post_code(0x21)
 	/* Set up the stack pointer. */
-	movl	$(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax
+	movl	$(STACK_BASE + STACK_SIZE - 4), %eax
 	movl	%eax, %esp
 
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
-	movl	%esp, %ebp
-	pushl	%eax
-
 before_romstage:
 	post_code(0x29)
 	/* Call romstage.c main function. */
diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c
index 2d2a87e..1aa773d 100644
--- a/src/mainboard/emulation/qemu-i440fx/romstage.c
+++ b/src/mainboard/emulation/qemu-i440fx/romstage.c
@@ -27,8 +27,8 @@
 
 #include "memory.c"
 
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+#include <cpu/qemu-x86/romstage.h>
+void main(void)
 {
 	int cbmem_was_initted;
 
diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c
index f6b7b63..bba605e 100644
--- a/src/mainboard/emulation/qemu-q35/romstage.c
+++ b/src/mainboard/emulation/qemu-q35/romstage.c
@@ -28,8 +28,8 @@
 
 #include "../qemu-i440fx/memory.c"
 
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+#include <cpu/qemu-x86/romstage.h>
+void main(void)
 {
 	int cbmem_was_initted;