[coreboot-gerrit] Patch set updated for coreboot: arch/x86/include: Rename bootblock_common to bootblock_romcc.h

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12867

-gerrit

commit 63ab98ffb21cd4ba34ff57f59e371dd64b5790b1
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Thu Jan 7 19:10:24 2016 -0800

    arch/x86/include: Rename bootblock_common to bootblock_romcc.h
    
    This header is only used for the bootblock compiled with ROMCC. As the
    follow-on patches introduce a bootblock which does not make use of
    ROMCC, rename this header to prevent confusion.
    
    Change-Id: Id29c5bc6928c11cc7cb922fcfac71e5a3dcd113c
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/arch/x86/bootblock_normal.c              |  2 +-
 src/arch/x86/bootblock_simple.c              |  2 +-
 src/arch/x86/include/arch/bootblock_common.h | 77 ----------------------------
 src/arch/x86/include/arch/bootblock_romcc.h  | 77 ++++++++++++++++++++++++++++
 4 files changed, 79 insertions(+), 79 deletions(-)

diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c
index a6a877c..061e3cb 100644
--- a/src/arch/x86/bootblock_normal.c
+++ b/src/arch/x86/bootblock_normal.c
@@ -1,5 +1,5 @@
 #include <smp/node.h>
-#include <arch/bootblock_common.h>
+#include <arch/bootblock_romcc.h>
 #include <pc80/mc146818rtc.h>
 #include <halt.h>
 
diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c
index 4bff360..b5eb414 100644
--- a/src/arch/x86/bootblock_simple.c
+++ b/src/arch/x86/bootblock_simple.c
@@ -1,5 +1,5 @@
 #include <smp/node.h>
-#include <arch/bootblock_common.h>
+#include <arch/bootblock_romcc.h>
 #include <halt.h>
 
 static void main(unsigned long bist)
diff --git a/src/arch/x86/include/arch/bootblock_common.h b/src/arch/x86/include/arch/bootblock_common.h
deleted file mode 100644
index 939ba08..0000000
--- a/src/arch/x86/include/arch/bootblock_common.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#include <arch/cbfs.h>
-#include <cpu/x86/lapic/boot_cpu.c>
-#include <pc80/mc146818rtc.h>
-
-#ifdef CONFIG_BOOTBLOCK_RESETS
-#include CONFIG_BOOTBLOCK_RESETS
-#endif
-
-#ifdef CONFIG_BOOTBLOCK_CPU_INIT
-#include CONFIG_BOOTBLOCK_CPU_INIT
-#endif
-#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#endif
-#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#endif
-
-#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT
-#include CONFIG_BOOTBLOCK_MAINBOARD_INIT
-#else
-static void bootblock_mainboard_init(void)
-{
-#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-	bootblock_northbridge_init();
-#endif
-#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-	bootblock_southbridge_init();
-#endif
-#ifdef CONFIG_BOOTBLOCK_CPU_INIT
-	bootblock_cpu_init();
-#endif
-}
-#endif
-
-#if CONFIG_USE_OPTION_TABLE
-static void sanitize_cmos(void)
-{
-	if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) {
-		unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default");
-		if (cmos_default) {
-			int i;
-			cmos_disable_rtc();
-			for (i = 14; i < 128; i++) {
-				cmos_write_inner(cmos_default[i], i);
-			}
-			cmos_enable_rtc();
-		}
-	}
-}
-#endif
-
-#if CONFIG_CMOS_POST
-static void cmos_post_init(void)
-{
-	u8 magic = CMOS_POST_BANK_0_MAGIC;
-
-	/* Switch to the other bank */
-	switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
-	case CMOS_POST_BANK_1_MAGIC:
-		break;
-	case CMOS_POST_BANK_0_MAGIC:
-		magic = CMOS_POST_BANK_1_MAGIC;
-		break;
-	default:
-		/* Initialize to zero */
-		cmos_write(0, CMOS_POST_BANK_0_OFFSET);
-		cmos_write(0, CMOS_POST_BANK_1_OFFSET);
-#if CONFIG_CMOS_POST_EXTRA
-		cmos_write32(CMOS_POST_BANK_0_EXTRA, 0);
-		cmos_write32(CMOS_POST_BANK_1_EXTRA, 0);
-#endif
-	}
-
-	cmos_write(magic, CMOS_POST_BANK_OFFSET);
-}
-#endif
diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h
new file mode 100644
index 0000000..939ba08
--- /dev/null
+++ b/src/arch/x86/include/arch/bootblock_romcc.h
@@ -0,0 +1,77 @@
+#include <arch/cbfs.h>
+#include <cpu/x86/lapic/boot_cpu.c>
+#include <pc80/mc146818rtc.h>
+
+#ifdef CONFIG_BOOTBLOCK_RESETS
+#include CONFIG_BOOTBLOCK_RESETS
+#endif
+
+#ifdef CONFIG_BOOTBLOCK_CPU_INIT
+#include CONFIG_BOOTBLOCK_CPU_INIT
+#endif
+#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
+#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
+#endif
+#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
+#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
+#endif
+
+#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT
+#include CONFIG_BOOTBLOCK_MAINBOARD_INIT
+#else
+static void bootblock_mainboard_init(void)
+{
+#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
+	bootblock_northbridge_init();
+#endif
+#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
+	bootblock_southbridge_init();
+#endif
+#ifdef CONFIG_BOOTBLOCK_CPU_INIT
+	bootblock_cpu_init();
+#endif
+}
+#endif
+
+#if CONFIG_USE_OPTION_TABLE
+static void sanitize_cmos(void)
+{
+	if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) {
+		unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default");
+		if (cmos_default) {
+			int i;
+			cmos_disable_rtc();
+			for (i = 14; i < 128; i++) {
+				cmos_write_inner(cmos_default[i], i);
+			}
+			cmos_enable_rtc();
+		}
+	}
+}
+#endif
+
+#if CONFIG_CMOS_POST
+static void cmos_post_init(void)
+{
+	u8 magic = CMOS_POST_BANK_0_MAGIC;
+
+	/* Switch to the other bank */
+	switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
+	case CMOS_POST_BANK_1_MAGIC:
+		break;
+	case CMOS_POST_BANK_0_MAGIC:
+		magic = CMOS_POST_BANK_1_MAGIC;
+		break;
+	default:
+		/* Initialize to zero */
+		cmos_write(0, CMOS_POST_BANK_0_OFFSET);
+		cmos_write(0, CMOS_POST_BANK_1_OFFSET);
+#if CONFIG_CMOS_POST_EXTRA
+		cmos_write32(CMOS_POST_BANK_0_EXTRA, 0);
+		cmos_write32(CMOS_POST_BANK_1_EXTRA, 0);
+#endif
+	}
+
+	cmos_write(magic, CMOS_POST_BANK_OFFSET);
+}
+#endif