[coreboot-gerrit] New patch to review for coreboot: cpu/qemu-x86: Move romstage assembly file to cpu directory
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Sat Jan 9 08:14:52 CET 2016
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12877
-gerrit
commit 071feff3499d7a997fbfb25a35d2c7fbffa13840
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date: Fri Jan 8 22:46:18 2016 -0800
cpu/qemu-x86: Move romstage assembly file to cpu directory
The romstage assembly file was implemented in qemu-i440fx mainboard
directory, but was also used by the qemu-q35 board via cpu_incs-y.
Consolidate this file into the cpu directory, as it is used by all
boards with this cpu.
Both qemu x86 boards succesfully execute ramstage.
Change-Id: I078da8c6d508571035e088d100fc18dae99e570b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
src/cpu/qemu-x86/Makefile.inc | 1 +
src/cpu/qemu-x86/romstage_entry.inc | 68 ++++++++++++++++++++++
src/mainboard/emulation/qemu-i440fx/Makefile.inc | 1 -
.../emulation/qemu-i440fx/cache_as_ram.inc | 68 ----------------------
src/mainboard/emulation/qemu-q35/Makefile.inc | 1 -
5 files changed, 69 insertions(+), 70 deletions(-)
diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc
index 0ed76f9..b6cf4f7 100644
--- a/src/cpu/qemu-x86/Makefile.inc
+++ b/src/cpu/qemu-x86/Makefile.inc
@@ -12,6 +12,7 @@
## GNU General Public License for more details.
##
+cpu_incs-y += $(src)/cpu/qemu-x86/romstage_entry.inc
bootblock-y += bootblock_asm.S
bootblock-y += bootblock.c
ramstage-y += qemu.c
diff --git a/src/cpu/qemu-x86/romstage_entry.inc b/src/cpu/qemu-x86/romstage_entry.inc
new file mode 100644
index 0000000..fcd2d3b
--- /dev/null
+++ b/src/cpu/qemu-x86/romstage_entry.inc
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+#include <cbmem.h>
+
+#define CACHE_AS_RAM_SIZE 0x10000
+#define CACHE_AS_RAM_BASE 0xd0000
+
+#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
+
+ /* Save the BIST result. */
+ movl %eax, %ebp
+
+cache_as_ram:
+ post_code(0x20)
+ /* Clear the cache memory region. This will also fill up the cache */
+ movl $CACHE_AS_RAM_BASE, %esi
+ movl %esi, %edi
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
+ // movl $0x23322332, %eax
+ xorl %eax, %eax
+ rep stosl
+
+ post_code(0x21)
+ /* Set up the stack pointer. */
+ movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax
+ movl %eax, %esp
+
+ /* Restore the BIST result. */
+ movl %ebp, %eax
+ movl %esp, %ebp
+ pushl %eax
+
+before_romstage:
+ post_code(0x29)
+ /* Call romstage.c main function. */
+ call main
+
+ post_code(0x30)
+
+__main:
+ post_code(POST_PREPARE_RAMSTAGE)
+ cld /* Clear direction flag. */
+
+ movl $CONFIG_RAMTOP, %esp
+ movl %esp, %ebp
+ call copy_and_run
+
+.Lhlt:
+ post_code(POST_DEAD_CODE)
+ hlt
+ jmp .Lhlt
diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc
index f9cf252..6ed3af1 100644
--- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc
+++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc
@@ -1,3 +1,2 @@
-cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
ramstage-y += northbridge.c
ramstage-y += fw_cfg.c
diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
deleted file mode 100644
index fcd2d3b..0000000
--- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/post_code.h>
-#include <cbmem.h>
-
-#define CACHE_AS_RAM_SIZE 0x10000
-#define CACHE_AS_RAM_BASE 0xd0000
-
-#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
-
- /* Save the BIST result. */
- movl %eax, %ebp
-
-cache_as_ram:
- post_code(0x20)
- /* Clear the cache memory region. This will also fill up the cache */
- movl $CACHE_AS_RAM_BASE, %esi
- movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
- // movl $0x23322332, %eax
- xorl %eax, %eax
- rep stosl
-
- post_code(0x21)
- /* Set up the stack pointer. */
- movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax
- movl %eax, %esp
-
- /* Restore the BIST result. */
- movl %ebp, %eax
- movl %esp, %ebp
- pushl %eax
-
-before_romstage:
- post_code(0x29)
- /* Call romstage.c main function. */
- call main
-
- post_code(0x30)
-
-__main:
- post_code(POST_PREPARE_RAMSTAGE)
- cld /* Clear direction flag. */
-
- movl $CONFIG_RAMTOP, %esp
- movl %esp, %ebp
- call copy_and_run
-
-.Lhlt:
- post_code(POST_DEAD_CODE)
- hlt
- jmp .Lhlt
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc
index fc4374c..e5f4b87 100644
--- a/src/mainboard/emulation/qemu-q35/Makefile.inc
+++ b/src/mainboard/emulation/qemu-q35/Makefile.inc
@@ -1,3 +1,2 @@
-cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
ramstage-y += ../qemu-i440fx/northbridge.c
ramstage-y += ../qemu-i440fx/fw_cfg.c
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