[coreboot-gerrit] Patch set updated for coreboot: intel/microcode: Move skylake's PRMRR check into mainline code

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12854

-gerrit

commit 5df2ca284c95aad52df63317588076fe78b25086
Author: Martin Roth <martinroth at google.com>
Date:   Wed Jan 6 16:24:49 2016 -0700

    intel/microcode: Move skylake's PRMRR check into mainline code
    
    Currently, the skylake build is breaking in ROMCC because of this
    code.  Moving it into the mainline microcode patch location fixes
    the issue with romcc and cleans up the code path significantly.
    
    Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c
    Signed-off-by: Martin Roth <martinroth at google.com>
---
 src/cpu/intel/microcode/microcode.c   | 11 +++++++++++
 src/include/cpu/x86/mtrr.h            |  1 +
 src/soc/intel/skylake/bootblock/cpu.c | 18 +-----------------
 3 files changed, 13 insertions(+), 17 deletions(-)

diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 35eff16..ada744e 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -23,6 +23,7 @@
 #endif
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/intel/microcode.h>
 #include <rules.h>
 
@@ -92,6 +93,16 @@ void intel_microcode_load_unlocked(const void *microcode_patch)
 	if (current_rev == m->rev)
 		return;
 
+	/* If PRMRR/SGX is supported the FIT microcode load step will set
+	 * msr 0x08b with the Patch revision id one less than the id in the
+	 * microcode binary. The PRMRR support is indicated in the MSR
+	 * MTRRCAP[12]. Check for this feature and avoid reloading the
+	 * same microcode during early cpu initialization.
+	 */
+	msr = rdmsr(MTRR_CAP_MSR);
+	if ((msr.lo & MTRR_CAP_PRMRR) && (current_rev == m->rev - 1))
+		return;
+
 #if ENV_RAMSTAGE
 	/*SoC specific check to update microcode*/
 	if (soc_skip_ucode_update(current_rev, m->rev)) {
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 8fd4261..950c7d4 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -11,6 +11,7 @@
 
 #define MTRR_CAP_MSR			0x0fe
 
+#define MTRR_CAP_PRMRR			(1 << 12)
 #define MTRR_CAP_SMRR			(1 << 11)
 #define MTRR_CAP_WC			(1 << 10)
 #define MTRR_CAP_FIX			(1 << 8)
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index bc9d638..0f1bcd7 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -173,23 +173,7 @@ static void check_for_clean_reset(void)
 
 static void patch_microcode(void)
 {
-	const struct microcode *patch;
-	u32 current_rev;
-	msr_t msr;
-
-	patch = intel_microcode_find();
-
-	current_rev = read_microcode_rev();
-
-	/* If PRMRR/SGX is supported the FIT microcode load step will set
-	 * msr 0x08b with the Patch revision id one less than the id in the
-	 * microcode binary. The PRMRR support is indicated in the MSR
-	 * MTRRCAP[12]. Check for this feature and avoid reloading the
-	 * same microcode during early cpu initialization.
-	 */
-	msr = rdmsr(MTRR_CAP_MSR);
-	if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1))
-		intel_update_microcode_from_cbfs();
+	intel_update_microcode_from_cbfs();
 }
 
 static void bootblock_cpu_init(void)