[coreboot-gerrit] Patch set updated for coreboot: viatool: Add VIA C3 MSRs

[Andrey Korolyov (andrey@xdel.ru)]

Andrey Korolyov (andrey at xdel.ru) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12851

-gerrit

commit cd76fc6337cf487a64297cca2fff3f2a53db66f6
Author: Andrey Korolyov <andrey at xdel.ru>
Date:   Wed Jan 6 19:26:26 2016 +0300

    viatool: Add VIA C3 MSRs
    
    Tested on C3/EPIA board and Linux x86
    
    Change-Id: I8df551f4b385ee8702af78df00169bdc8e180925
    Signed-off-by: Andrey Korolyov <andrey at xdel.ru>
---
 util/viatool/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/util/viatool/cpu.c b/util/viatool/cpu.c
index 9aaa050..4bf1271 100644
--- a/util/viatool/cpu.c
+++ b/util/viatool/cpu.c
@@ -185,6 +185,48 @@ int print_intel_core_msrs(void)
 		//{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO
 	};
 
+	/* VIA C3 Nehemiah */
+	static const msr_entry_t model69x_global_msrs[] = {
+		{ 0x0010, "IA32_TIME_STAMP_COUNTER" },
+		{ 0x002a, "EBL_CR_POWERON" },
+		{ 0x00c1, "PERFCTR0" },
+		{ 0x00c2, "PERFCTR1" },
+		{ 0x011e, "BBL_CR_CTL3" },
+		{ 0x0186, "EVNTSEL0" },
+		{ 0x0187, "EVNTSEL1" },
+		{ 0x0200, "IA32_MTRR_PHYSBASE0" },
+		{ 0x0201, "IA32_MTRR_PHYSMASK0" },
+		{ 0x0202, "IA32_MTRR_PHYSBASE1" },
+		{ 0x0203, "IA32_MTRR_PHYSMASK1" },
+		{ 0x0204, "IA32_MTRR_PHYSBASE2" },
+		{ 0x0205, "IA32_MTRR_PHYSMASK2" },
+		{ 0x0206, "IA32_MTRR_PHYSBASE3" },
+		{ 0x0207, "IA32_MTRR_PHYSMASK3" },
+		{ 0x0208, "IA32_MTRR_PHYSBASE4" },
+		{ 0x0209, "IA32_MTRR_PHYSMASK4" },
+		{ 0x020a, "IA32_MTRR_PHYSBASE5" },
+		{ 0x020b, "IA32_MTRR_PHYSMASK5" },
+		{ 0x020c, "IA32_MTRR_PHYSBASE6" },
+		{ 0x020d, "IA32_MTRR_PHYSMASK6" },
+		{ 0x020e, "IA32_MTRR_PHYSBASE7" },
+		{ 0x020f, "IA32_MTRR_PHYSMASK7" },
+		{ 0x0250, "IA32_MTRR_FIX64K_00000" },
+		{ 0x0258, "IA32_MTRR_FIX16K_80000" },
+		{ 0x0259, "IA32_MTRR_FIX16K_A0000" },
+		{ 0x0268, "IA32_MTRR_FIX4K_C0000" },
+		{ 0x0269, "IA32_MTRR_FIX4K_C8000" },
+		{ 0x026a, "IA32_MTRR_FIX4K_D0000" },
+		{ 0x026b, "IA32_MTRR_FIX4K_D8000" },
+		{ 0x026c, "IA32_MTRR_FIX4K_E0000" },
+		{ 0x026d, "IA32_MTRR_FIX4K_E8000" },
+		{ 0x026e, "IA32_MTRR_FIX4K_F0000" },
+		{ 0x026f, "IA32_MTRR_FIX4K_F8000" },
+		{ 0x02ff, "IA32_MTRR_DEF_TYPE" },
+		{ 0x1107, "FCR" },
+		{ 0x1108, "FCR2" },
+// WRITE ONLY	{ 0x1109, "FCR3" },
+	};
+
 	static const msr_entry_t model6bx_global_msrs[] = {
 		{ 0x0010, "IA32_TIME_STAMP_COUNTER" },
 		{ 0x0017, "IA32_PLATFORM_ID" },
@@ -894,6 +936,7 @@ int print_intel_core_msrs(void)
 
 	cpu_t cpulist[] = {
 		{ 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 },
+		{ 0x00690, model69x_global_msrs, ARRAY_SIZE(model69x_global_msrs), NULL, 0 },
 		{ 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
 		{ 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
 		{ 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },