[coreboot-gerrit] Patch set updated for coreboot: sb/amd/sr5650: Correctly locate CPU MMIO resource

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12821

-gerrit

commit 32684e32f8f61cd06d3a51a56ef076fe5ba9d7ae
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Fri Jan 1 23:30:42 2016 -0600

    sb/amd/sr5650: Correctly locate CPU MMIO resource
    
    The code committed in GIT hash 1eaaa0 [southbridge/amd/sr5650:
    Add MCFG ACPI table support] did not correctly locate the CPU MMIO
    resource, leading to failures with operating systems and firmware
    when the PCI extended configuration space option was activated.
    
    Search for the CPU MMIO resource on all domains below the root device.
    
    Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/southbridge/amd/sr5650/sr5650.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index d4355d6..5fd5e2f 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -35,13 +35,15 @@ extern void set_pcie_dereset(void);
 extern void set_pcie_reset(void);
 
 struct resource * sr5650_retrieve_cpu_mmio_resource() {
-	device_t cpu;
+	device_t domain;
+	struct device *sibling;
+	struct bus *link;
 	struct resource *res;
 
-	for (cpu = all_devices; cpu; cpu = cpu->next) {
-		if (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)
+	for (domain = all_devices; domain; domain = domain->next) {
+		if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN)
 			continue;
-		res = probe_resource(cpu->bus->dev, 0xc0010058);
+		res = probe_resource(domain->bus->dev, 0xc0010058);
 		if (res)
 			return res;
 	}