[coreboot-gerrit] New patch to review for coreboot: [WIP] Required to test EXAR superIO chip XR28V382

[Patrick Agrain (patrick.agrain@al-enterprise.com)]

Patrick Agrain (patrick.agrain at al-enterprise.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17988

-gerrit

commit 66d19a95abc0fc8b2670c1cb05bf8e2825bd5949
Author: Patrick Agrain <patrick.agrain at al-enterprise.com>
Date:   Thu Dec 29 01:17:48 2016 -0800

    [WIP] Required to test EXAR superIO chip XR28V382
    
    These modifications have been performed to be able to test the EXAR
    superIO chip XR28V382 on an Intel Mohon Peak CRB.
    This should also allow reviewers to check if nothing is missing.
    DO NOT MERGE.
    
    Change-Id: Ib76d5dff822ab9e6524dd11cd9dd026bef7315cd
    Signed-off-by: Patrick Agrain <patrick.agrain at al-enterprise.com>
---
 src/mainboard/intel/mohonpeak/Kconfig       | 3 ++-
 src/mainboard/intel/mohonpeak/devicetree.cb | 8 ++++++++
 src/mainboard/intel/mohonpeak/romstage.c    | 1 +
 src/superio/Makefile.inc                    | 1 +
 4 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig
index 38c9976..18b3a75 100644
--- a/src/mainboard/intel/mohonpeak/Kconfig
+++ b/src/mainboard/intel/mohonpeak/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select POST_IO
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
+	select SUPERIO_EXAR_XR28V382
 
 config MAINBOARD_DIR
 	string
@@ -44,7 +45,7 @@ config CACHE_ROM_SIZE_OVERRIDE
 
 config FSP_FILE
 	string
-	default "../intel/fsp/rangeley/FvFsp.bin"
+	default "./intel/fsp/FvFsp.bin"
 
 config CBFS_SIZE
 	hex
diff --git a/src/mainboard/intel/mohonpeak/devicetree.cb b/src/mainboard/intel/mohonpeak/devicetree.cb
index 1df54d3..c0e977f 100644
--- a/src/mainboard/intel/mohonpeak/devicetree.cb
+++ b/src/mainboard/intel/mohonpeak/devicetree.cb
@@ -58,6 +58,14 @@ chip northbridge/intel/fsp_rangeley
 			device pci 17.0 on end # SATA 2.0
 			device pci 18.0 on end # SATA 3.0
 			device pci 1f.0 on end # LPC bridge
+				chip superio/exar/xr28v382 # Super I/O
+				  device pnp 2e.0 on       # COM 1
+					io 0x60 = 0x3f8
+					irq 0x70 = 4
+				  end
+				  device pnp 2e.1 off end  # COM 2
+				  device pnp 2e.8 off end  # Watchdog
+				end
 			device pci 1f.3 on end # SMBus 0
 		end
 	end
diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c
index c7c78e2..671b5f5 100644
--- a/src/mainboard/intel/mohonpeak/romstage.c
+++ b/src/mainboard/intel/mohonpeak/romstage.c
@@ -24,6 +24,7 @@
 #include <southbridge/intel/fsp_rangeley/gpio.h>
 #include <southbridge/intel/fsp_rangeley/romstage.h>
 #include <arch/cpu.h>
+#include <superio/exar/xr28v382/xr28v382.h>
 #include "gpio.h"
 
 static void interrupt_routing_config(void)
diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc
index 5fc0ecd..89d2ff4 100644
--- a/src/superio/Makefile.inc
+++ b/src/superio/Makefile.inc
@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
+subdirs-y += exar
 subdirs-y += fintek
 subdirs-y += intel
 subdirs-y += ite