[coreboot-gerrit] New patch to review for coreboot: superio/w83627dhg: Add power_on_fail cmos option
Arthur Heymans (arthur@aheymans.xyz)
gerrit at coreboot.org
Sun Dec 25 11:02:45 CET 2016
Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17963
-gerrit
commit 8f6a6a8a4fd1f226125e64b03c29f87c155e68c3
Author: Arthur Heymans <arthur at aheymans.xyz>
Date: Sun Dec 25 10:58:02 2016 +0100
superio/w83627dhg: Add power_on_fail cmos option
This change allows to configure the power-loss control bits
of the superio.
An entry to cmos.default was added if the motherboard already featured
such a file.
Change-Id: I4eaa8ad61f6d89cbfd541fc6e1b06710ce41b7a4
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
src/mainboard/asrock/939a785gmh/cmos.layout | 5 ++++-
src/mainboard/asus/p5gc-mx/cmos.default | 3 ++-
src/mainboard/asus/p5gc-mx/cmos.layout | 8 +++++++-
src/mainboard/kontron/kt690/cmos.layout | 5 ++++-
src/mainboard/lippert/toucan-af/cmos.layout | 5 ++++-
src/mainboard/supermicro/h8qgi/cmos.layout | 5 ++++-
src/mainboard/supermicro/h8scm/cmos.layout | 5 ++++-
src/mainboard/tyan/s8226/cmos.layout | 5 ++++-
src/superio/winbond/w83627dhg/superio.c | 18 ++++++++++++++++++
9 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/src/mainboard/asrock/939a785gmh/cmos.layout b/src/mainboard/asrock/939a785gmh/cmos.layout
index 0d4f95e..cb91284 100644
--- a/src/mainboard/asrock/939a785gmh/cmos.layout
+++ b/src/mainboard/asrock/939a785gmh/cmos.layout
@@ -25,7 +25,7 @@ entries
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
+400 2 e 7 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
@@ -59,6 +59,9 @@ enumerations
6 7 Info
6 8 Debug
6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
8 0 DDR400
8 1 DDR333
8 2 DDR266
diff --git a/src/mainboard/asus/p5gc-mx/cmos.default b/src/mainboard/asus/p5gc-mx/cmos.default
index ab7aac1..3a53775 100644
--- a/src/mainboard/asus/p5gc-mx/cmos.default
+++ b/src/mainboard/asus/p5gc-mx/cmos.default
@@ -4,4 +4,5 @@ debug_level=Spew
hyper_threading=Enable
nmi=Enable
boot_devices=''
-gfx_uma_size=8M
\ No newline at end of file
+gfx_uma_size=8M
+power_on_after_fail=Disable
\ No newline at end of file
diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout
index eaf51bb..feeb3b1 100644
--- a/src/mainboard/asus/p5gc-mx/cmos.layout
+++ b/src/mainboard/asus/p5gc-mx/cmos.layout
@@ -32,7 +32,10 @@ entries
# coreboot config options: cpu
400 1 e 2 hyper_threading
-#401 7 r 0 unused
+#401 4 r 0 unused
+
+# coreboot config option: superio
+405 2 e 7 power_on_after_fail
# coreboot config options: southbridge
408 1 e 1 nmi
@@ -83,6 +86,9 @@ enumerations
6 7 Info
6 8 Debug
6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
11 0 1M
11 1 4M
11 2 8M
diff --git a/src/mainboard/kontron/kt690/cmos.layout b/src/mainboard/kontron/kt690/cmos.layout
index 93aa445..9c9088c 100644
--- a/src/mainboard/kontron/kt690/cmos.layout
+++ b/src/mainboard/kontron/kt690/cmos.layout
@@ -25,7 +25,7 @@ entries
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
+400 2 e 7 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
@@ -59,6 +59,9 @@ enumerations
6 7 Info
6 8 Debug
6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
8 0 DDR400
8 1 DDR333
8 2 DDR266
diff --git a/src/mainboard/lippert/toucan-af/cmos.layout b/src/mainboard/lippert/toucan-af/cmos.layout
index ca3d9e5..219ee7c 100644
--- a/src/mainboard/lippert/toucan-af/cmos.layout
+++ b/src/mainboard/lippert/toucan-af/cmos.layout
@@ -24,7 +24,7 @@ entries
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
+400 2 e 7 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
@@ -58,6 +58,9 @@ enumerations
6 7 Info
6 8 Debug
6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout
index ca3d9e5..219ee7c 100644
--- a/src/mainboard/supermicro/h8qgi/cmos.layout
+++ b/src/mainboard/supermicro/h8qgi/cmos.layout
@@ -24,7 +24,7 @@ entries
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
+400 2 e 7 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
@@ -58,6 +58,9 @@ enumerations
6 7 Info
6 8 Debug
6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
diff --git a/src/mainboard/supermicro/h8scm/cmos.layout b/src/mainboard/supermicro/h8scm/cmos.layout
index ca3d9e5..219ee7c 100644
--- a/src/mainboard/supermicro/h8scm/cmos.layout
+++ b/src/mainboard/supermicro/h8scm/cmos.layout
@@ -24,7 +24,7 @@ entries
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
+400 2 e 7 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
@@ -58,6 +58,9 @@ enumerations
6 7 Info
6 8 Debug
6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
diff --git a/src/mainboard/tyan/s8226/cmos.layout b/src/mainboard/tyan/s8226/cmos.layout
index ca3d9e5..219ee7c 100644
--- a/src/mainboard/tyan/s8226/cmos.layout
+++ b/src/mainboard/tyan/s8226/cmos.layout
@@ -24,7 +24,7 @@ entries
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
+400 2 e 7 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
@@ -58,6 +58,9 @@ enumerations
6 7 Info
6 8 Debug
6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c
index 5a1502a..ba38c90 100644
--- a/src/superio/winbond/w83627dhg/superio.c
+++ b/src/superio/winbond/w83627dhg/superio.c
@@ -21,6 +21,21 @@
#include <stdlib.h>
#include "w83627dhg.h"
+static void init_acpi(struct device *dev)
+{
+ u8 value;
+ int power_on = 0;
+
+ get_option(&power_on, "power_on_after_fail");
+ pnp_enter_conf_mode(dev);
+ pnp_set_logical_device(dev);
+ value = pnp_read_config(dev, 0xe4);
+ value &= ~(3 << 5);
+ value |= (power_on << 5);
+ pnp_write_config(dev, 0xe4, value);
+ pnp_exit_conf_mode(dev);
+}
+
static void w83627dhg_enable_UR2(struct device *dev)
{
u8 reg8;
@@ -45,6 +60,9 @@ static void w83627dhg_init(struct device *dev)
case W83627DHG_KBC:
pc_keyboard_init(NO_AUX_DEVICE);
break;
+ case W83627DHG_ACPI:
+ init_acpi(dev);
+ break;
}
}
More information about the coreboot-gerrit
mailing list