[coreboot-gerrit] New patch to review for coreboot: soc/intel/skylake: Initialize LPSS UART based on DRIVERS_UART_8250MEM_32
Subrata Banik (subrata.banik@intel.com)
gerrit at coreboot.org
Fri Dec 23 12:27:51 CET 2016
Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17956
-gerrit
commit b991c6a682c0c5913421d37fec7c296d8d7211a3
Author: Subrata Banik <subrata.banik at intel.com>
Date: Fri Dec 23 16:42:55 2016 +0530
soc/intel/skylake: Initialize LPSS UART based on DRIVERS_UART_8250MEM_32
pch_uart_init and base address assignment should be done
based on DRIVERS_UART_8250MEM_32 config selection. Enabling
legacy UART for debug on RVP does not require additional UART2
programming.
TEST=Build and boot SKL RVP to have serial log through legacy UART.
Change-Id: Iea4f204275c6eb78646f510a7097f7cf8470b576
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
src/soc/intel/skylake/bootblock/bootblock.c | 2 ++
src/soc/intel/skylake/uart_debug.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index 93a031f..9bfa8b1 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -29,8 +29,10 @@ void bootblock_soc_early_init(void)
bootblock_cpu_init();
pch_early_iorange_init();
+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)
if (IS_ENABLED(CONFIG_UART_DEBUG))
pch_uart_init();
+#endif
}
void bootblock_soc_init(void)
diff --git a/src/soc/intel/skylake/uart_debug.c b/src/soc/intel/skylake/uart_debug.c
index f3d576b..e52f717 100644
--- a/src/soc/intel/skylake/uart_debug.c
+++ b/src/soc/intel/skylake/uart_debug.c
@@ -18,9 +18,11 @@
#include <soc/iomap.h>
#include <soc/serialio.h>
+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)
uintptr_t uart_platform_base(int idx)
{
/* Same base address for all debug port usage. In reality UART2
* is currently only supported. */
return UART_DEBUG_BASE_ADDRESS;
}
+#endif
More information about the coreboot-gerrit
mailing list