[coreboot-gerrit] Patch merged into coreboot/master: drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 0a5971c91bac57970e3f3229b8cda735a17b3a67
Author: Brenton Dong <brenton.m.dong at intel.com>
Date:   Tue Oct 18 11:35:15 2016 -0700

    drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support
    
    FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for
    Cache-As-Ram initialization and teardown.  Add fsp2_0 driver
    support for TempRamInit & TempRamExit APIs.
    
    Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
    is correctly set up and torn down using the FSP v2.0 APIs
    without coreboot implementation of CAR init/teardown.
    
    Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2
    Signed-off-by: Brenton Dong <brenton.m.dong at intel.com>
    Reviewed-on: https://review.coreboot.org/17062
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/17062 for details.

-gerrit