[coreboot-gerrit] Patch merged into coreboot/master: intel cache-as-ram: Move DCACHE_RAM_BASE
gerrit at coreboot.org
gerrit at coreboot.org
Sun Dec 18 20:52:05 CET 2016
the following patch was just integrated into master:
commit c86c6b33e8ca32ffa0f0d7e30f35f1fb31fe3b4a
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Fri Dec 9 17:43:27 2016 +0200
intel cache-as-ram: Move DCACHE_RAM_BASE
Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.
As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.
There are no reasons to have this as board-specific setting.
Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
See https://review.coreboot.org/17806 for details.
-gerrit
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