[coreboot-gerrit] Patch merged into coreboot/master: amd/gardenia: Correct SPD AGESA callout
gerrit at coreboot.org
gerrit at coreboot.org
Fri Dec 16 23:02:15 CET 2016
the following patch was just integrated into master:
commit 4bbea904170196b4cc59031a8ada7901def934fb
Author: Marshall Dawson <marshalldawson3rd at gmail.com>
Date: Sat Oct 8 09:53:58 2016 -0600
amd/gardenia: Correct SPD AGESA callout
Gardenia makes no special considerations for a board_id regarding
SPD access and addressing. Remove this from the source and use
the standard AGESA call.
Make SPD address changes to devicetree.cb. Note that Gardenia is
designed to be a two channel, single DIMM/channel system (some SKUs
with two DIMMs on the second channel). However, this port is for
the Stoney processor which is a single channel. As a result, the
second DIMM slot is not usable. A future improvement could involve
a port using a different processor, with unique devicetree files
for each.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
Original-Reviewed-by: Marc Jones <marcj303 at gmail.com>
(cherry picked from commit 77511f98f819dfe08c3ed16ebc11e1b328bdca15)
Change-Id: Id00c2be83340ceeec043ec86e96779e6bf46ae7b
Signed-off-by: Marc Jones <marcj303 at gmail.com>
Reviewed-on: https://review.coreboot.org/17219
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth at google.com>
See https://review.coreboot.org/17219 for details.
-gerrit
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