[coreboot-gerrit] New patch to review for coreboot: google/eve: Enable native mode for UART pins in bootblock

[Duncan Laurie (dlaurie@chromium.org)]

Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17893

-gerrit

commit 20e8d14b4b43d68ced7b6c30a74be03e2eca76cb
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Dec 14 16:57:37 2016 -0800

    google/eve: Enable native mode for UART pins in bootblock
    
    Put the UART pins into native mode in bootblock so they are not
    floating when we try to communicate with H1 over I2C.  Without
    a serial console enabled BIOS these pins were not configured
    until ramstage.
    
    BUG=chrome-os-partner:60935
    TEST=Boot Eve board without serial console and H1 TPM enabled
    
    Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/eve/gpio.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
index c7a5e46..34ae3a4 100644
--- a/src/mainboard/google/eve/gpio.h
+++ b/src/mainboard/google/eve/gpio.h
@@ -225,6 +225,10 @@ static const struct pad_config early_gpio_table[] = {
 /* I2C1_SCL */		PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */
 /* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
 /* SATAXPCI0 */		PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */
+
+/* Ensure UART pins are in native mode for H1 */
+/* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
+/* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 };
 
 #endif