[coreboot-gerrit] Patch set updated for coreboot: soc/glk: Add i2c init using common code

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17826

-gerrit

commit 400403d25b0dbbf49eb8ed60430be26e9ff15958
Author: Hannah Williams <hannah.williams at intel.com>
Date:   Fri Nov 18 15:27:38 2016 -0800

    soc/glk: Add i2c init using common code
    
    Change-Id: I6ec2f007a9fca82c880d1886e10f97afd9dfb073
    Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
 src/soc/intel/glk/Makefile.inc |  2 --
 src/soc/intel/glk/chip.h       | 11 +----------
 src/soc/intel/glk/i2c.c        | 18 +++---------------
 3 files changed, 4 insertions(+), 27 deletions(-)

diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc
index 6aa5123..32c9d10 100644
--- a/src/soc/intel/glk/Makefile.inc
+++ b/src/soc/intel/glk/Makefile.inc
@@ -26,7 +26,6 @@ romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
 romstage-y += gpio.c
 romstage-y += heci.c
-romstage-y += i2c_early.c
 romstage-y += itss.c
 romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 romstage-y += lpc_lib.c
@@ -82,7 +81,6 @@ postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 postcar-y += tsc_freq.c
 
 verstage-y += car.c
-verstage-y += i2c_early.c
 verstage-y += heci.c
 verstage-y += memmap.c
 verstage-y += mmap_boot.c
diff --git a/src/soc/intel/glk/chip.h b/src/soc/intel/glk/chip.h
index 40247db..b0c0fd2 100644
--- a/src/soc/intel/glk/chip.h
+++ b/src/soc/intel/glk/chip.h
@@ -28,15 +28,6 @@
 #define CLKREQ_DISABLED		0xf
 #define GLK_I2C_DEV_MAX		8
 
-struct glk_i2c_config {
-	/* Bus should be enabled prior to ramstage with temporary base */
-	int early_init;
-	/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
-	enum i2c_speed speed;
-	/* Specific bus speed configuration */
-	struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT];
-};
-
 /* Serial IRQ control. SERIRQ_QUIET is the default (0). */
 enum serirq_mode {
 	SERIRQ_QUIET,
@@ -95,7 +86,7 @@ struct soc_intel_glk_config {
 	enum serirq_mode serirq_mode;
 
 	/* I2C bus configuration */
-	struct glk_i2c_config i2c[GLK_I2C_DEV_MAX];
+	struct lpss_i2c_bus_config i2c[GLK_I2C_DEV_MAX];
 
 	uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
 	uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
diff --git a/src/soc/intel/glk/i2c.c b/src/soc/intel/glk/i2c.c
index ade8602..14535a1 100644
--- a/src/soc/intel/glk/i2c.c
+++ b/src/soc/intel/glk/i2c.c
@@ -60,24 +60,12 @@ static int i2c_dev_to_bus(struct device *dev)
 static void i2c_dev_init(struct device *dev)
 {
 	struct soc_intel_glk_config *config = dev->chip_info;
-	const struct lpss_i2c_speed_config *sptr;
-	enum i2c_speed speed;
-	int i, bus = i2c_dev_to_bus(dev);
+	int bus = i2c_dev_to_bus(dev);
 
 	if (!config || bus < 0)
 		return;
 
-	speed = config->i2c[bus].speed ? : I2C_SPEED_FAST;
-	lpss_i2c_init(bus, speed);
-
-	/* Apply custom speed config if it has been set by the board */
-	for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) {
-		sptr = &config->i2c[bus].speed_config[i];
-		if (sptr->speed == speed) {
-			lpss_i2c_set_speed_config(bus, sptr);
-			break;
-		}
-	}
+	lpss_i2c_init(bus, &config->i2c[bus]);
 }
 
 static void i2c_fill_ssdt(struct device *dev)
@@ -89,7 +77,7 @@ static void i2c_fill_ssdt(struct device *dev)
 		return;
 
 	acpigen_write_scope(acpi_device_path(dev));
-	lpss_i2c_acpi_fill_ssdt(config->i2c[bus].speed_config);
+	lpss_i2c_acpi_fill_ssdt(bus, &config->i2c[bus]);
 	acpigen_pop_len();
 }