[coreboot-gerrit] Patch set updated for coreboot: Set the fsb timer correctly for Netburst CPUs
Arthur Heymans (arthur@aheymans.xyz)
gerrit at coreboot.org
Tue Dec 13 16:13:49 CET 2016
Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17832
-gerrit
commit 1d86cdbd827895a42eaf100eae700a70cd6e482a
Author: Arthur Heymans <arthur at aheymans.xyz>
Date: Tue Dec 13 15:21:24 2016 +0100
Set the fsb timer correctly for Netburst CPUs
On Netburst (Pentium 4) the fsb cannot be read from
MSR_FSB_FREQ (msr 0xcd). One has to use msr 0x2c instead.
Change-Id: I0beccba2e4a8ec5cd23537b2207f9c49a040fd73
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
src/cpu/x86/lapic/apic_timer.c | 59 +++++++++++++++++++++++++++---------------
1 file changed, 38 insertions(+), 21 deletions(-)
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index 1930ec4..5df7d86 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -47,31 +47,48 @@ static int set_timer_fsb(void)
struct cpuinfo_x86 c;
int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 };
+ int f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 };
get_fms(&c, cpuid_eax(1));
- if (c.x86 != 6)
+ if (c.x86 == 6) {
+
+ switch (c.x86_model) {
+ case 0xe: /* Core Solo/Duo */
+ case 0x1c: /* Atom */
+ car_set_var(g_timer_fsb,
+ core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
+ break;
+ case 0xf: /* Core 2 or Xeon */
+ case 0x17: /* Enhanced Core */
+ car_set_var(g_timer_fsb,
+ core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
+ break;
+ case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
+ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
+ case 0x3c: /* Haswell BCLK fixed at 100MHz */
+ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
+ car_set_var(g_timer_fsb, 100);
+ break;
+ default:
+ car_set_var(g_timer_fsb, 200);
+ break;
+ }
+ } else if (c.x86 == 0xf) /* Netburst */
+ switch (c.x86_model) {
+ case 0x2:
+ car_set_var(g_timer_fsb,
+ f2x_fsb_fsb[(rdmsr(0x2c).lo >> 16) & 7]);
+ break;
+ case 0x3:
+ case 0x4:
+ case 0x6:
+ car_set_var(g_timer_fsb,
+ core2_fsb[(rdmsr(0x2c).lo >> 16) & 7]);
+ break;
+
+ else
return -1;
- switch (c.x86_model) {
- case 0xe: /* Core Solo/Duo */
- case 0x1c: /* Atom */
- car_set_var(g_timer_fsb, core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
- break;
- case 0xf: /* Core 2 or Xeon */
- case 0x17: /* Enhanced Core */
- car_set_var(g_timer_fsb, core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
- break;
- case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
- case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
- case 0x3c: /* Haswell BCLK fixed at 100MHz */
- case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
- car_set_var(g_timer_fsb, 100);
- break;
- default:
- car_set_var(g_timer_fsb, 200);
- break;
- }
-
return 0;
}
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