[coreboot-gerrit] Patch set updated for coreboot: soc/glk: select config CACHE_MRC_SETTINGS
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Tue Dec 13 05:53:07 CET 2016
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17821
-gerrit
commit e58d8e1a9368b081d2700a96fe1ba49ad9395f56
Author: Hannah Williams <hannah.williams at intel.com>
Date: Mon Oct 31 14:09:55 2016 -0700
soc/glk: select config CACHE_MRC_SETTINGS
Change-Id: Id214aadc3e508ecbfceda8ecc4c1e4ddd15d8895
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
src/soc/intel/glk/Kconfig | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig
index 9d40e3b..f79d81f 100644
--- a/src/soc/intel/glk/Kconfig
+++ b/src/soc/intel/glk/Kconfig
@@ -61,6 +61,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_GFX_OPREGION
select ADD_VBT_DATA_FILE
select SOC_INTEL_COMMON_RESET
+ select CACHE_MRC_SETTINGS
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
@@ -125,6 +126,7 @@ config CONSOLE_UART_BASE_ADDRESS
hex "MMIO base address for UART"
default 0xde000000
+
config SOC_UART_DEBUG
bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE."
default n
@@ -156,10 +158,6 @@ config VERSTAGE_ADDR
help
The base address (in CAR) where verstage should be linked
-config CACHE_MRC_SETTINGS
- bool
- default y
-
config FSP_M_ADDR
hex
default 0xfef40000
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