[coreboot-gerrit] Patch set updated for coreboot: intel MMA: Enable MMA with FSP2.0
Pratikkumar V Prajapati (pratikkumar.v.prajapati@intel.com)
gerrit at coreboot.org
Fri Dec 9 23:03:16 CET 2016
Pratikkumar V Prajapati (pratikkumar.v.prajapati at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17496
-gerrit
commit a925af9fa47f9325ac477fa7a17a0450cfc8d0e2
Author: Pratik Prajapati <pratikkumar.v.prajapati at intel.com>
Date: Fri Nov 18 14:36:34 2016 -0800
intel MMA: Enable MMA with FSP2.0
- Separate mma code for fsp1.1 and fsp2.0
and restructuring the code
- common code is placed in mma.c and mma.h
- mma_fsp<ver>.h and fsp<ver>/mma_core.c contains
fsp version specific code.
- whole MMA feature is guarded by CONFIG_MMA flag.
Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati at intel.com>
---
src/drivers/intel/fsp1_1/Makefile.inc | 2 +
src/drivers/intel/fsp1_1/include/fsp/romstage.h | 2 +
src/drivers/intel/fsp1_1/mma_core.c | 53 +++++
src/drivers/intel/fsp1_1/raminit.c | 1 -
src/drivers/intel/fsp2_0/Makefile.inc | 2 +
src/drivers/intel/fsp2_0/include/fsp/api.h | 3 +
src/drivers/intel/fsp2_0/memory_init.c | 3 +
src/drivers/intel/fsp2_0/mma_core.c | 49 +++++
src/soc/intel/common/Kconfig | 5 +-
src/soc/intel/common/mma.c | 221 +++++++++------------
src/soc/intel/common/mma.h | 21 +-
src/soc/intel/skylake/include/fsp11/soc/romstage.h | 8 +
src/soc/intel/skylake/include/fsp20/soc/romstage.h | 9 +-
src/soc/intel/skylake/romstage/romstage.c | 23 +++
src/soc/intel/skylake/romstage/romstage_fsp20.c | 21 ++
15 files changed, 285 insertions(+), 138 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 4ea23f3..4088293 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -31,6 +31,7 @@ romstage-y += romstage.c
romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
romstage-y += stack.c
romstage-y += stage_cache.c
+romstage-$(CONFIG_MMA) += mma_core.c
ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
ramstage-y += fsp_relocate.c
@@ -39,6 +40,7 @@ ramstage-y += hob.c
ramstage-y += ramstage.c
ramstage-y += stage_cache.c
ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
+ramstage-$(CONFIG_MMA) += mma_core.c
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index 4683f5e..bf36efc 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -76,6 +76,8 @@ void mainboard_save_dimm_info(struct romstage_params *params);
void mainboard_add_dimm_info(struct romstage_params *params,
struct memory_info *mem_info,
int channel, int dimm, int index);
+/* Initialize memory margin analysis settings. */
+void setup_mma(MEMORY_INIT_UPD *memory_upd);
void raminit(struct romstage_params *params);
void report_memory_config(void);
void romstage_common(struct romstage_params *params);
diff --git a/src/drivers/intel/fsp1_1/mma_core.c b/src/drivers/intel/fsp1_1/mma_core.c
new file mode 100644
index 0000000..dce4f78
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/mma_core.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <fsp/soc_binding.h>
+#include <soc/intel/common/mma.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+#define FSP_MMA_RESULTS_GUID { 0x8f4e928, 0xf5f, 0x46d4, \
+ { 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 } }
+
+int fsp_locate_mma_results(const void **mma_hob, size_t *mma_hob_size)
+{
+ const void *mma_hob_start;
+ const EFI_GUID mma_results_guid = FSP_MMA_RESULTS_GUID;
+
+ mma_hob_start = get_first_guid_hob(&mma_results_guid);
+ if (!mma_hob_start)
+ return -1;
+ *mma_hob = GET_GUID_HOB_DATA(mma_hob_start);
+ *mma_hob_size = GET_HOB_LENGTH(mma_hob);
+
+ if (!(*mma_hob_size) || !(*mma_hob))
+ return -1;
+ return 0;
+}
+
+void setup_mma(MEMORY_INIT_UPD *memory_cfg)
+{
+ struct mma_config_param mma_cfg;
+
+ if (mma_locate_param(&mma_cfg)) {
+ printk(BIOS_DEBUG, "MMA: set up failed\n");
+ return;
+ }
+
+ soc_update_memory_params_for_mma(memory_cfg, &mma_cfg);
+ printk(BIOS_DEBUG, "MMA: set up completed successfully\n");
+}
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index eca8934..4b07ede 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -21,7 +21,6 @@
#include <fsp/util.h>
#include <lib.h> /* hexdump */
#include <reset.h>
-#include <soc/intel/common/mma.h>
#include <string.h>
#include <timestamp.h>
#include <vboot/vboot_common.h>
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index beeec7c..ad654b9 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -24,6 +24,7 @@ romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c
romstage-y += util.c
romstage-y += memory_init.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+romstage-$(CONFIG_MMA) += mma_core.c
ramstage-y += debug.c
ramstage-y += graphics.c
@@ -36,6 +37,7 @@ ramstage-y += silicon_init.c
ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
ramstage-y += util.c
+ramstage-$(CONFIG_MMA) += mma_core.c
postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index a8445ba..c56ba32 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -40,6 +40,9 @@ enum fsp_notify_phase {
void fsp_memory_init(bool s3wake);
void fsp_silicon_init(bool s3wake);
+/* Initialize memory margin analysis settings. */
+void setup_mma(FSP_M_CONFIG *memory_cfg);
+
/* Callbacks for updating stage-specific parameters */
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 283b179..63a5733 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -313,6 +313,9 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
/* Give SoC and mainboard a chance to update the UPD */
platform_fsp_memory_init_params_cb(&fspm_upd, hdr->fsp_revision);
+ if (IS_ENABLED(CONFIG_MMA))
+ setup_mma(&fspm_upd.FspmConfig);
+
/* Call FspMemoryInit */
fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd);
diff --git a/src/drivers/intel/fsp2_0/mma_core.c b/src/drivers/intel/fsp2_0/mma_core.c
new file mode 100644
index 0000000..213be35
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/mma_core.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <fsp/soc_binding.h>
+#include <soc/intel/common/mma.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+static const uint8_t mma_results_uuid[16] = { 0x28, 0xe9, 0xf4, 0x08,
+ 0x5f, 0x0f, 0xd4, 0x46,
+ 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 };
+
+int fsp_locate_mma_results(const void **mma_hob, size_t *mma_hob_size)
+{
+ *mma_hob_size = 0;
+ *mma_hob = fsp_find_extension_hob_by_guid(mma_results_uuid,
+ mma_hob_size);
+
+ if (!(*mma_hob_size) || !(*mma_hob))
+ return -1;
+ return 0;
+}
+
+void setup_mma(FSP_M_CONFIG *memory_cfg)
+{
+ struct mma_config_param mma_cfg;
+
+ if (mma_locate_param(&mma_cfg)) {
+ printk(BIOS_DEBUG, "MMA: set up failed\n");
+ return;
+ }
+
+ soc_update_memory_params_for_mma(memory_cfg, &mma_cfg);
+ printk(BIOS_DEBUG, "MMA: set up completed successfully\n");
+}
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 23dd601..1cc856e 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -83,10 +83,11 @@ config SOC_INTEL_COMMON_LPSS_I2C_DEBUG
when debugging I2C drivers.
config MMA
- bool "enable MMA (Memory Margin Analysis) support"
+ bool "Enable MMA (Memory Margin Analysis) support for Intel Core"
default n
+ depends on PLATFORM_USES_FSP2_0 || PLATFORM_USES_FSP1_1
help
- Set this option to y to enable MMA (Memory Margin Analysis) support
+ Set this option to y to enable MMA (Memory Margin Analysis) support
config MMA_BLOBS_PATH
string "Path to MMA blobs"
diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c
index 87d8e5c..b9569ff 100644
--- a/src/soc/intel/common/mma.c
+++ b/src/soc/intel/common/mma.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,38 +13,34 @@
* GNU General Public License for more details.
*/
-#include <boot/coreboot_tables.h>
#include <bootstate.h>
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
-#include <lib.h>
-#include "mma.h"
-#include <soc/romstage.h>
-#include <string.h>
-#include <fmap.h>
-
-#define MMA_TEST_METADATA_FILENAME "mma_test_metadata.bin"
-#define MMA_TEST_NAME_TAG "MMA_TEST_NAME"
-#define MMA_TEST_PARAM_TAG "MMA_TEST_PARAM"
+#include <soc/intel/common/mma.h>
+
+#define MMA_TEST_METADATA_FILENAME "mma_test_metadata.bin"
+#define MMA_TEST_NAME_TAG "MMA_TEST_NAME"
+#define MMA_TEST_PARAM_TAG "MMA_TEST_PARAM"
+#define TEST_NAME_MAX_SIZE 30
+#define TEST_PARAM_MAX_SIZE 100
+#define MMA_DATA_SIGNATURE (('M' << 0) | ('M' << 8) | \
+ ('A' << 16) | ('D' << 24))
#define MMA_CBFS_REGION "COREBOOT"
-#define TEST_NAME_MAX_SIZE 30
-#define TEST_PARAM_MAX_SIZE 100
-#define FSP_MMA_RESULTS_GUID { 0x8f4e928, 0xf5f, 0x46d4, \
- { 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 } }
-#define MMA_DATA_SIGNATURE (('M'<<0)|('M'<<8)|('A'<<16)|('D'<<24))
struct mma_data_container {
- u32 mma_signature; // "MMAD"
- u8 mma_data[0]; // Variable size, platform/run time dependent.
+ uint32_t mma_signature; /* "MMAD" */
+ uint8_t mma_data[0]; /* Variable size, platform/run time dependent. */
} __attribute__ ((packed));
/*
-Format of the MMA test metadata file, stored under CBFS
-MMA_TEST_NAME=xxxxxx.efi;MMA_TEST_PARAM=xxxxxx.bin;
-*/
+ * Format of the MMA test metadata file, stored under CBFS
+ * MMA_TEST_NAME=xxxxxx.efi;MMA_TEST_PARAM=xxxxxx.bin;
+ */
-/* Returns index in haystack after 'LABEL=' string is found, < 0 on error. */
+/* Returns index in haystack after 'LABEL='
+ * string is found, < 0 on error.
+ */
static int find_label(const char *haystack, size_t haystack_sz,
const char *label)
{
@@ -72,12 +68,13 @@ static int find_label(const char *haystack, size_t haystack_sz,
return i + label_sz + 1;
}
+
/*
* Fill in value in dest field located by LABEL=.
- * Returns 0 on success, < 0 on error.
+ * Returns 0 on success, < 0 on error.
*/
static int label_value(const char *haystack, size_t haystack_sz,
- const char *label, char *dest, size_t dest_sz)
+ const char *label, char *dest, size_t dest_sz)
{
size_t val_begin;
size_t val_end;
@@ -114,159 +111,121 @@ static int label_value(const char *haystack, size_t haystack_sz,
return 0;
}
-static void *cbfs_locate_file_in_region(const char *region_name, const char *file_name,
- uint32_t file_type, uint32_t *file_size)
-{
- struct region_device rdev;
- struct cbfsf fh;
-
- if (file_size != NULL)
- *file_size = 0;
-
- if (fmap_locate_area_as_rdev(region_name, &rdev) == 0) {
- if (cbfs_locate(&fh, &rdev, file_name, &file_type) == 0) {
- if (file_size != NULL)
- *file_size = region_device_sz(&fh.data);
- return rdev_mmap_full(&fh.data);
- } else
- printk(BIOS_DEBUG, "%s file not found in %s region\n",
- file_name, region_name);
- } else
- printk(BIOS_DEBUG,"%s region not found while looking for %s\n", region_name,
- file_name);
-
- return NULL;
-}
-
-void setup_mma(MEMORY_INIT_UPD *memory_params)
+int mma_locate_param(struct mma_config_param *mma_cfg)
{
- void *mma_test_metadata, *mma_test_content, *mma_test_param;
- size_t mma_test_metadata_file_len, mma_test_content_file_len,
- mma_test_param_file_len;
+ void *mma_test_metadata;
+ size_t mma_test_metadata_file_len;
char test_filename[TEST_NAME_MAX_SIZE],
- test_param_filename[TEST_PARAM_MAX_SIZE];
+ test_param_filename[TEST_PARAM_MAX_SIZE];
+ struct cbfsf metadata_fh, test_content_fh, test_param_fh;
+ uint32_t mma_type = CBFS_TYPE_MMA;
+ uint32_t efi_type = CBFS_TYPE_EFI;
+ bool metadata_parse_flag = true;
- printk(BIOS_DEBUG, "Entry setup_mma\n");
+ printk(BIOS_DEBUG, "MMA: Entry %s\n", __func__);
- memory_params->MmaTestContentPtr = 0;
- memory_params->MmaTestContentSize = 0;
- memory_params->MmaTestConfigPtr = 0;
- memory_params->MmaTestConfigSize = 0;
+ if (cbfs_locate_file_in_region(&metadata_fh, MMA_CBFS_REGION,
+ MMA_TEST_METADATA_FILENAME, &mma_type)) {
+ printk(BIOS_DEBUG, "MMA: Failed to locate %s\n",
+ MMA_TEST_METADATA_FILENAME);
+ return -1;
+ }
- mma_test_metadata = cbfs_locate_file_in_region(MMA_CBFS_REGION,
- MMA_TEST_METADATA_FILENAME, CBFS_TYPE_MMA,
- &mma_test_metadata_file_len);
+ mma_test_metadata = rdev_mmap_full(&metadata_fh.data);
+ mma_test_metadata_file_len = region_device_sz(&metadata_fh.data);
- if (!mma_test_metadata) {
- printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s\n",
+ if (!mma_test_metadata || !mma_test_metadata_file_len) {
+ printk(BIOS_DEBUG, "MMA: Failed to read %s\n",
MMA_TEST_METADATA_FILENAME);
- return;
+ metadata_parse_flag = false;
}
- if (label_value(mma_test_metadata, mma_test_metadata_file_len,
- MMA_TEST_NAME_TAG, test_filename, TEST_NAME_MAX_SIZE)) {
- printk(BIOS_DEBUG, "MMA setup failed : Failed to get %s",
- MMA_TEST_NAME_TAG);
- return;
+ if (metadata_parse_flag &&
+ label_value(mma_test_metadata, mma_test_metadata_file_len,
+ MMA_TEST_NAME_TAG, test_filename,
+ TEST_NAME_MAX_SIZE)) {
+ printk(BIOS_DEBUG, "MMA: Failed to get %s\n",
+ MMA_TEST_NAME_TAG);
+ metadata_parse_flag = false;
}
- if (label_value(mma_test_metadata, mma_test_metadata_file_len,
+ if (metadata_parse_flag &&
+ label_value(mma_test_metadata, mma_test_metadata_file_len,
MMA_TEST_PARAM_TAG, test_param_filename,
- TEST_PARAM_MAX_SIZE)) {
- printk(BIOS_DEBUG, "MMA setup failed : Failed to get %s",
+ TEST_PARAM_MAX_SIZE)) {
+ printk(BIOS_DEBUG, "MMA: Failed to get %s\n",
MMA_TEST_PARAM_TAG);
- return;
+ metadata_parse_flag = false;
}
- printk(BIOS_DEBUG, "Got MMA_TEST_NAME=%s MMA_TEST_PARAM=%s\n",
+ rdev_munmap(&metadata_fh.data, mma_test_metadata);
+
+ if (!metadata_parse_flag)
+ return -1;
+
+ printk(BIOS_DEBUG, "MMA: Got MMA_TEST_NAME=%s MMA_TEST_PARAM=%s\n",
test_filename, test_param_filename);
- mma_test_content = cbfs_locate_file_in_region(MMA_CBFS_REGION,
- test_filename, CBFS_TYPE_EFI,
- &mma_test_content_file_len);
- if (!mma_test_content) {
- printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s.\n",
- test_filename);
- return;
+ if (cbfs_locate_file_in_region(&test_content_fh, MMA_CBFS_REGION,
+ test_filename, &efi_type)) {
+ printk(BIOS_DEBUG, "MMA: Failed to locate %s\n",
+ test_filename);
+ return -1;
}
- mma_test_param = cbfs_locate_file_in_region(MMA_CBFS_REGION,
- test_param_filename, CBFS_TYPE_MMA,
- &mma_test_param_file_len);
- if (!mma_test_param) {
- printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s.\n",
+ cbfs_file_data(&mma_cfg->test_content, &test_content_fh);
+
+ if (cbfs_locate_file_in_region(&test_param_fh, MMA_CBFS_REGION,
+ test_param_filename, &mma_type)) {
+ printk(BIOS_DEBUG, "MMA: Failed to locate %s\n",
test_param_filename);
- return;
+ return -1;
}
- memory_params->MmaTestContentPtr = (uintptr_t) mma_test_content;
- memory_params->MmaTestContentSize = mma_test_content_file_len;
- memory_params->MmaTestConfigPtr = (uintptr_t) mma_test_param;
- memory_params->MmaTestConfigSize = mma_test_param_file_len;
- memory_params->MrcFastBoot = 0x00;
- memory_params->SaGv = 0x02;
-
- printk(BIOS_DEBUG, "MMA Test name %s\n", test_filename);
- printk(BIOS_DEBUG, "MMA Test Config name %s\n", test_param_filename);
- printk(BIOS_DEBUG, "MMA passing following memory_params\n");
- printk(BIOS_DEBUG, "memory_params->MmaTestContentPtr = %0x\n",
- memory_params->MmaTestContentPtr);
- printk(BIOS_DEBUG, "memory_params->MmaTestContentSize = %d\n",
- memory_params->MmaTestContentSize);
- printk(BIOS_DEBUG, "memory_params->MmaTestConfigPtr = %0x\n",
- memory_params->MmaTestConfigPtr);
- printk(BIOS_DEBUG, "memory_params->MmaTestConfigSize = %d\n",
- memory_params->MmaTestConfigSize);
- printk(BIOS_DEBUG, "memory_params->MrcFastBoot = %d\n",
- memory_params->MrcFastBoot);
- printk(BIOS_DEBUG, "memory_params->SaGv = %d\n",
- memory_params->SaGv);
-
- printk(BIOS_DEBUG, "MMA setup successfully\n");
+ cbfs_file_data(&mma_cfg->test_param, &test_param_fh);
+
+ printk(BIOS_DEBUG, "MMA: %s exit success\n", __func__);
+
+ return 0;
}
static void save_mma_results_data(void *unused)
{
- void *mma_results_hob;
- u32 mma_hob_size;
- u32 *mma_hob_data;
+ const void *mma_hob;
+ size_t mma_hob_size;
struct mma_data_container *mma_data;
- int cbmem_size;
-
- const EFI_GUID mma_results_guid = FSP_MMA_RESULTS_GUID;
+ size_t mma_data_size;
- printk(BIOS_DEBUG, "Entry save_mma_results_data MMA save data.\n");
+ printk(BIOS_DEBUG, "MMA: Entry %s\n", __func__);
- mma_results_hob = get_first_guid_hob(&mma_results_guid);
- if (mma_results_hob == NULL) {
+ if (fsp_locate_mma_results(&mma_hob, &mma_hob_size)) {
printk(BIOS_DEBUG,
- "MMA results data Hob not present\n");
+ "MMA: results data Hob not present\n");
return;
}
- mma_hob_data = GET_GUID_HOB_DATA(mma_results_hob);
- mma_hob_size = GET_HOB_LENGTH(mma_results_hob);
- cbmem_size = ALIGN(mma_hob_size, 16) +
+ mma_data_size = ALIGN(mma_hob_size, 16) +
sizeof(struct mma_data_container);
- mma_data = cbmem_add(CBMEM_ID_MMA_DATA, cbmem_size);
+
+ mma_data = cbmem_add(CBMEM_ID_MMA_DATA, mma_data_size);
if (mma_data == NULL) {
printk(BIOS_DEBUG,
- "CBMEM was not available to save the MMA data.\n");
+ "MMA: CBMEM was not available to save the MMA data.\n");
return;
}
/*clear the mma_data before coping the actual data */
- memset(mma_data, 0, cbmem_size);
+ memset(mma_data, 0, mma_data_size);
printk(BIOS_DEBUG,
- "Copy MMA DATA to HOB(src addr %p, dest addr %p, %u bytes)\n",
- mma_hob_data, mma_data, mma_hob_size);
+ "MMA: copy MMA data to CBMEM(src 0x%p, dest 0x%p, %u bytes)\n",
+ mma_hob, mma_data, mma_hob_size);
mma_data->mma_signature = MMA_DATA_SIGNATURE;
- memcpy(mma_data->mma_data, mma_hob_data, mma_hob_size);
+ memcpy(mma_data->mma_data, mma_hob, mma_hob_size);
- printk(BIOS_DEBUG, "write MMA results data to cbmem success\n");
+ printk(BIOS_DEBUG, "MMA: %s exit successfully\n", __func__);
}
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
diff --git a/src/soc/intel/common/mma.h b/src/soc/intel/common/mma.h
index f1c91e2..20dfc15 100644
--- a/src/soc/intel/common/mma.h
+++ b/src/soc/intel/common/mma.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -16,8 +16,23 @@
#ifndef _SOC_MMA_H_
#define _SOC_MMA_H_
-#include <fsp/soc_binding.h>
+#include <stdint.h>
+#include <commonlib/region.h>
-void setup_mma(MEMORY_INIT_UPD *memory_params);
+struct mma_config_param {
+ struct region_device test_content;
+ struct region_device test_param;
+};
+
+/* Locate mma metadata in CBFS, parse, find and fill rdev for
+ * mma test content and test param.
+ * Returns 0 on success, < 0 on failure.
+ */
+int mma_locate_param(struct mma_config_param *mma_cfg);
+/* Locate the MMA hob from the FSP Hob list, This is implemented
+ * specific to FSP version.
+ * Returns 0 on success, < 0 on failure.
+ */
+int fsp_locate_mma_results(const void **mma_hob, size_t *mma_hob_size);
#endif
diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
index 6c40bd6..7ea437c 100644
--- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
@@ -18,6 +18,8 @@
#define _SOC_ROMSTAGE_H_
#include <fsp/romstage.h>
+#include <fsp/uefi_binding.h>
+#include <soc/intel/common/mma.h>
void systemagent_early_init(void);
void intel_early_me_status(void);
@@ -26,5 +28,11 @@ int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read_wpsr(u8 *sr);
void mainboard_fill_spd_data(struct pei_data *pei_data);
+/* update the memory config param for mma. set location and size of
+ * MMA test content, test param and set SOC specifig memory params like
+ * Fastboot mode, SAGV
+ */
+void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,
+ struct mma_config_param *mma_cfg);
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
index 08753f1..f14e8a4 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
@@ -19,13 +19,20 @@
#include <arch/cpu.h>
#include <fsp/api.h>
+#include <fsp/soc_binding.h>
+#include <soc/intel/common/mma.h>
asmlinkage void *car_stage_c_entry(void);
void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read_wpsr(u8 *sr);
-
+/* update the memory config param for mma. set location and size of
+ * MMA test content, test param and set SOC specifig memory params like
+ * Fastboot mode, SAGV
+ */
+void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
+ struct mma_config_param *mma_cfg);
/* Board type */
enum board_type {
BOARD_TYPE_MOBILE = 0,
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 97c6a45..6f78c49 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -21,6 +21,7 @@
#include <arch/cbfs.h>
#include <arch/stages.h>
#include <arch/early_variables.h>
+#include <assert.h>
#include <cbmem.h>
#include <chip.h>
#include <console/console.h>
@@ -31,6 +32,7 @@
#include <elog.h>
#include <reset.h>
#include <romstage_handoff.h>
+#include <soc/intel/common/mma.h>
#include <soc/pci_devs.h>
#include <soc/pei_wrapper.h>
#include <soc/pm.h>
@@ -97,6 +99,27 @@ void soc_memory_init_params(struct romstage_params *params,
}
}
+void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,
+ struct mma_config_param *mma_cfg)
+{
+ /* This is SOC specific implementation. Boot media
+ * is memory mapped for Skylake and Kabylake (SPI).
+ */
+
+ assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+
+ memory_cfg->MmaTestContentPtr =
+ (uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
+ memory_cfg->MmaTestContentSize =
+ region_device_sz(&mma_cfg->test_content);
+ memory_cfg->MmaTestConfigPtr =
+ (uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
+ memory_cfg->MmaTestConfigSize =
+ region_device_sz(&mma_cfg->test_param);
+ memory_cfg->MrcFastBoot = 0x00;
+ memory_cfg->SaGv = 0x02;
+}
+
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
MEMORY_INIT_UPD *new)
{
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 73d726c..ce1c10b 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -26,6 +26,7 @@
#include <device/pci_def.h>
#include <fsp/util.h>
#include <fsp/memmap.h>
+#include <soc/intel/common/mma.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@@ -165,6 +166,26 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mainboard_memory_init_params(mupd);
}
+void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
+ struct mma_config_param *mma_cfg)
+{
+ /* This is SOC specific implementation. Boot media
+ * is memory mapped for Skylake and Kabylake (SPI).
+ */
+ assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+
+ memory_cfg->MmaTestContentPtr =
+ (uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
+ memory_cfg->MmaTestContentSize =
+ region_device_sz(&mma_cfg->test_content);
+ memory_cfg->MmaTestConfigPtr =
+ (uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
+ memory_cfg->MmaTestConfigSize =
+ region_device_sz(&mma_cfg->test_param);
+ memory_cfg->MrcFastBoot = 0x00;
+ memory_cfg->SaGv = 0x02;
+}
+
__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd)
{
/* Do nothing */
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