[coreboot-gerrit] New patch to review for coreboot: soc/broadwell: set EM4/EM5 registers based on cdclk

[Matt DeVillier (matt.devillier@gmail.com)]

Matt DeVillier (matt.devillier at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17718

-gerrit

commit 867cacf4b88696a212d0c03240cbb2c8ff4d3c83
Author: Matt DeVillier <matt.devillier at gmail.com>
Date:   Wed Nov 16 23:37:43 2016 -0600

    soc/broadwell: set EM4/EM5 registers based on cdclk
    
    The EM4/EM5 registers in the mini-HD audio device must be set based
    on the GPU cdclk value in order for HDMI audio to function properly.
    Add variables to save the correct values when initializing the GPU,
    and accessor functions to retrieve them in order to set the registers
    when initializing the mini-HD device.
    
    Also fix a GPU-type check which meant to cap ULX GPUs cdclk value but
    incorrectly checked for ULT instead.
    
    Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba
    Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
 src/soc/intel/broadwell/igd.c             | 22 ++++++++++++++++++----
 src/soc/intel/broadwell/include/soc/igd.h | 22 ++++++++++++++++++++++
 src/soc/intel/broadwell/minihd.c          |  5 +++++
 3 files changed, 45 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index ccb1e93..9c05876 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -38,6 +38,12 @@
 #define GT_CDCLK_540		2
 #define GT_CDCLK_675		3
 
+static u32 reg_em4;
+static u32 reg_em5;
+
+u32 igd_get_reg_em4(void) { return reg_em4; }
+u32 igd_get_reg_em5(void) { return reg_em5; }
+
 struct reg_script haswell_early_init_script[] = {
 	/* Enable Force Wake */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020),
@@ -398,6 +404,7 @@ static void igd_cdclk_init_haswell(struct device *dev)
 static void igd_cdclk_init_broadwell(struct device *dev)
 {
 	config_t *conf = dev->chip_info;
+	int devid = pci_read_config16(dev, PCI_DEVICE_ID);
 	int cdclk = conf->cdclk;
 	u32 dpdiv, lpcll, pwctl, cdset;
 
@@ -407,8 +414,7 @@ static void igd_cdclk_init_broadwell(struct device *dev)
 	gtt_write(0x138124, 0x80000018);
 
 	/* Poll GT driver mailbox for run/busy clear */
-	if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
-		cdclk = GT_CDCLK_450;
+	gtt_poll(0x138124, (1 << 31), (0 << 31));
 
 	if (gtt_read(0x42014) & 0x1000000) {
 		/* If CD clock is fixed then set to 450MHz */
@@ -421,8 +427,8 @@ static void igd_cdclk_init_broadwell(struct device *dev)
 			cdclk = GT_CDCLK_675;
 	}
 
-	/* CD clock frequency 675MHz not supported on ULT */
-	if (cpu_is_ult() && cdclk == GT_CDCLK_675)
+	/* CD clock frequency 675MHz not supported on ULX */
+	if (devid == IGD_BROADWELL_Y_GT2 && cdclk == GT_CDCLK_675)
 		cdclk = GT_CDCLK_540;
 
 	/* Set variables based on CD Clock setting */
@@ -432,24 +438,32 @@ static void igd_cdclk_init_broadwell(struct device *dev)
 		lpcll = (1 << 27);
 		pwctl = 2;
 		dpdiv = 169;
+		reg_em4 = 16;
+		reg_em5 = 225;
 		break;
 	case GT_CDCLK_450:
 		cdset = 449;
 		lpcll = 0;
 		pwctl = 0;
 		dpdiv = 225;
+		reg_em4 = 4;
+		reg_em5 = 75;
 		break;
 	case GT_CDCLK_540:
 		cdset = 539;
 		lpcll = (1 << 26);
 		pwctl = 1;
 		dpdiv = 270;
+		reg_em4 = 4;
+		reg_em5 = 90;
 		break;
 	case GT_CDCLK_675:
 		cdset = 674;
 		lpcll = (1 << 26) | (1 << 27);
 		pwctl = 3;
 		dpdiv = 338;
+		reg_em4 = 8;
+		reg_em5 = 225;
 	default:
 		return;
 	}
diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/soc/intel/broadwell/include/soc/igd.h
new file mode 100644
index 0000000..a0db5ef
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/igd.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_BROADWELL_GMA_H
+#define SOC_INTEL_BROADWELL_GMA_H
+
+u32 igd_get_reg_em4(void);
+u32 igd_get_reg_em5(void);
+
+#endif /* SOC_INTEL_BROADWELL_GMA_H */
\ No newline at end of file
diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c
index 5014b08..a9fc3d6 100644
--- a/src/soc/intel/broadwell/minihd.c
+++ b/src/soc/intel/broadwell/minihd.c
@@ -25,6 +25,7 @@
 #include <stdlib.h>
 #include <soc/intel/common/hda_verb.h>
 #include <soc/ramstage.h>
+#include <soc/igd.h>
 
 static const u32 minihd_verb_table[] = {
 	/* coreboot specific header */
@@ -101,6 +102,10 @@ static void minihd_init(struct device *dev)
 					       minihd_verb_table);
 		}
 	}
+
+	/* Set EM4/EM5 registers */
+	write32(base + 0x0100c, igd_get_reg_em4());
+	write32(base + 0x01010, igd_get_reg_em5());
 }
 
 static struct device_operations minihd_ops = {