[coreboot-gerrit] Patch set updated for coreboot: intel/nehalem post-car: Use postcar_frame for MTRR setup
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Thu Dec 1 14:42:26 CET 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15793
-gerrit
commit e4881b38c55595183b37807c76e504558142cce3
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Fri Jul 22 22:52:14 2016 +0300
intel/nehalem post-car: Use postcar_frame for MTRR setup
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE
and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions
are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM.
Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/model_2065x/cache_as_ram.inc | 63 ++++++++++++++++++-----------
src/mainboard/lenovo/x201/romstage.c | 1 -
src/mainboard/packardbell/ms2290/romstage.c | 1 -
src/northbridge/intel/nehalem/Kconfig | 1 +
src/northbridge/intel/nehalem/ram_calc.c | 32 ++++++++++++++-
5 files changed, 72 insertions(+), 26 deletions(-)
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index 93d6907..b7c59fa 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -170,8 +170,8 @@ before_romstage:
/* Call romstage.c main function. */
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down.
- */
+ * after cache-as-ram is torn down. It also contains the information
+ * for setting up MTRRs. */
movl %eax, %esp
post_code(0x30)
@@ -220,31 +220,48 @@ before_romstage:
post_code(0x38)
- /* Enable Write Back and Speculative Reads for the first MB
- * and ramstage.
- */
+ /* Clear all of the variable MTRRs. */
+ popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx
- movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
- xorl %edx, %edx
+ clr %eax
+ clr %edx
+
+1:
+ testl %ebx, %ebx
+ jz 1f
+ wrmsr /* Write MTRR base. */
+ inc %ecx
+ wrmsr /* Write MTRR mask. */
+ inc %ecx
+ dec %ebx
+ jmp 1b
+
+1:
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+2:
+ testl %ebx, %ebx
+ jz 2f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
wrmsr
- movl $MTRR_PHYS_MASK(0), %ecx
- movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
- movl $CPU_PHYSMASK_HI, %edx // 36bit address space
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
wrmsr
+ inc %ecx
-#if CACHE_ROM_SIZE
- /* Enable Caching and speculative Reads for the
- * complete ROM now that we actually have RAM.
- */
- movl $MTRR_PHYS_BASE(1), %ecx
- movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
- xorl %edx, %edx
- wrmsr
- movl $MTRR_PHYS_MASK(1), %ecx
- movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
- movl $CPU_PHYSMASK_HI, %edx
- wrmsr
-#endif
+ dec %ebx
+ jmp 2b
+2:
post_code(0x39)
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 2bfa19c..7b8d7f9 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -282,7 +282,6 @@ void mainboard_romstage_entry(unsigned long bist)
* this is not a resume. In that case we just create the cbmem toc.
*/
if (s3resume) {
- acpi_prepare_for_resume();
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index 92ee021..04c9513 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -272,7 +272,6 @@ void mainboard_romstage_entry(unsigned long bist)
* this is not a resume. In that case we just create the cbmem toc.
*/
if (s3resume) {
- acpi_prepare_for_resume();
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index eee9405..b373107 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_NEHALEM
select INTEL_EDID
select TSC_MONOTONIC_TIMER
select INTEL_GMA_ACPI
+ select RELOCATABLE_RAMSTAGE
select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
if NORTHBRIDGE_INTEL_NEHALEM
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index 4d73ee9..407fc64 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -1,6 +1,7 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2012 ChromeOS Authors
* Copyright (C) 2013 Vladimir Serbinenko.
*
* This program is free software; you can redistribute it and/or modify
@@ -15,9 +16,13 @@
#define __SIMPLE_DEVICE__
+#include <arch/cpu.h>
#include <arch/io.h>
#include <cbmem.h>
+#include <console/console.h>
#include <cpu/intel/romstage.h>
+#include <cpu/x86/mtrr.h>
+#include <program_loading.h>
#include "nehalem.h"
static uintptr_t smm_region_start(void)
@@ -32,7 +37,32 @@ void *cbmem_top(void)
return (void *) smm_region_start();
}
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
void *setup_stack_and_mtrrs(void)
{
- return (void*)CONFIG_RAMTOP;
+ struct postcar_frame pcf;
+ uint32_t top_of_ram;
+
+ if (postcar_frame_init(&pcf, 1*KiB))
+ die("Unable to initialize postcar frame.\n");
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+ /* Cache at least 8 MiB below the top of ram, and at most 8 MiB
+ * above top of the ram. This satisfies MTRR alignment requirement
+ * with different TSEG size configurations.
+ */
+ top_of_ram = ALIGN_DOWN((uint32_t)cbmem_top(), 8*MiB);
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
+
+ /* Save the number of MTRRs to setup. Return the stack location
+ * pointing to the number of MTRRs.
+ */
+ return postcar_commit_mtrrs(&pcf);
}
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