[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
Brenton Dong (brenton.m.dong@intel.com)
gerrit at coreboot.org
Thu Dec 1 00:01:59 CET 2016
Brenton Dong (brenton.m.dong at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17063
-gerrit
commit 70a88539143e294e17c825fbebd4d16f1241929b
Author: Brenton Dong <brenton.m.dong at intel.com>
Date: Tue Oct 18 13:57:54 2016 -0700
soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize
& tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to
ApolloLake SoC when CONFIG_FSP_CAR is enabled.
Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.
Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25
Signed-off-by: Brenton Dong <brenton.m.dong at intel.com>
---
src/arch/x86/exit_car.S | 5 +-
src/arch/x86/postcar.c | 8 +-
src/soc/intel/apollolake/Makefile.inc | 14 +++-
.../intel/apollolake/bootblock/cache_as_ram_fsp.S | 98 ++++++++++++++++++++++
src/soc/intel/apollolake/exit_car_fsp.S | 47 +++++++++++
5 files changed, 164 insertions(+), 8 deletions(-)
diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
index 5c62c92..61287d2 100644
--- a/src/arch/x86/exit_car.S
+++ b/src/arch/x86/exit_car.S
@@ -19,7 +19,8 @@
.section ".module_parameters", "aw", @progbits
/* stack_top indicates the stack to pull MTRR information from. */
-stack_top:
+.global post_car_stack_top
+post_car_stack_top:
.long 0
.long 0
@@ -38,7 +39,7 @@ _start:
invd
/* Set up new stack. */
- mov stack_top, %esp
+ mov post_car_stack_top, %esp
/*
* Honor variable MTRR information pushed on the stack with the
diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c
index c4c9cda..34a4335 100644
--- a/src/arch/x86/postcar.c
+++ b/src/arch/x86/postcar.c
@@ -22,15 +22,15 @@
void main(void)
{
+ /* Call TempRamExit FSP API if enabled. */
+ if (IS_ENABLED(CONFIG_FSP_CAR))
+ fsp_temp_ram_exit();
+
console_init();
/* Recover cbmem so infrastruture using it is functional. */
cbmem_initialize();
- /* Call TempRamExit FSP API if enabled. */
- if (IS_ENABLED(CONFIG_FSP_CAR))
- fsp_temp_ram_exit();
-
/* Display the MTRRs */
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
soc_display_mtrrs();
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 4f867e1..9ae5569 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/tsc
subdirs-y += ../../../cpu/x86/cache
bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/cache_as_ram.S
bootblock-y += bootblock/bootblock.c
bootblock-y += car.c
bootblock-y += gpio.c
@@ -22,6 +21,12 @@ bootblock-y += spi.c
bootblock-y += tsc_freq.c
bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+ifeq ($(CONFIG_FSP_CAR),y)
+bootblock-y += bootblock/cache_as_ram_fsp.S
+else
+bootblock-y += bootblock/cache_as_ram.S
+endif
+
romstage-y += car.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
romstage-y += gpio.c
@@ -75,13 +80,18 @@ ramstage-y += sram.c
ramstage-y += spi.c
ramstage-y += xhci.c
-postcar-y += exit_car.S
postcar-y += memmap.c
postcar-y += mmap_boot.c
postcar-y += spi.c
postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
postcar-y += tsc_freq.c
+ifeq ($(CONFIG_FSP_CAR),y)
+postcar-y += exit_car_fsp.S
+else
+postcar-y += exit_car.S
+endif
+
verstage-y += car.c
verstage-y += i2c_early.c
verstage-y += heci.c
diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S
new file mode 100644
index 0000000..31cdb35
--- /dev/null
+++ b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_def.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/cr.h>
+#include <cpu/x86/post_code.h>
+#include <soc/cpu.h>
+
+#include <../../../arch/x86/walkcbfs.S>
+
+#define FSP_HDR_OFFSET 0x94
+
+.global bootblock_pre_c_entry
+bootblock_pre_c_entry:
+
+.global cache_as_ram
+cache_as_ram:
+ post_code(0x21)
+
+ /* find fsp in cbfs */
+ lea fsp_name, %esi
+ mov $1f, %esp
+ jmp walkcbfs_asm
+1:
+ cmp $0, %eax
+ jz .halt_forever
+ mov CBFS_FILE_OFFSET(%eax), %ebx
+ bswap %ebx
+ add %eax, %ebx
+ add FSP_HDR_OFFSET, %ebx
+
+ /*
+ * ebx = FSP INFO HEADER
+ * Calculate entry into FSP
+ */
+ mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */
+ add 0x1c(%ebx), %eax /* add the FSP ImageBase */
+
+ /*
+ * Pass early init variables on a fake stack (no memory yet)
+ * as well as the return location
+ */
+ lea CAR_init_stack, %esp
+
+ /* call FSP binary to setup temporary stack */
+ jmp *%eax
+
+CAR_init_done:
+
+ /* Setup bootblock stack */
+ mov %edx, %esp
+
+ /* clear CAR_GLOBAL area as it is not shared */
+ cld
+ xor %eax, %eax
+ movl $(_car_global_end), %ecx
+ movl $(_car_global_start), %edi
+ sub %edi, %ecx
+ rep stosl
+ nop
+
+ /* We can call into C functions now */
+ call bootblock_c_entry
+
+ /* Never reached */
+
+.halt_forever:
+ post_code(POST_DEAD_CODE)
+ hlt
+ jmp .halt_forever
+
+CAR_init_params:
+ .long 0 /* Microcode Location */
+ .long 0 /* Microcode Length */
+ .long 0xFFFFFFFF - CONFIG_CBFS_SIZE + 1 /* Firmware Location */
+ .long CONFIG_CBFS_SIZE /* Total Firmware Length */
+
+CAR_init_stack:
+ .long CAR_init_done
+ .long CAR_init_params
+
+fsp_name:
+ .ascii "blobs/fspt.bin\x00"
diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/apollolake/exit_car_fsp.S
new file mode 100644
index 0000000..32c276c
--- /dev/null
+++ b/src/soc/intel/apollolake/exit_car_fsp.S
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cr.h>
+#include <soc/cpu.h>
+
+/*
+ * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.
+ * This version of chipset_teardown_car sets up the stack, then bypasses
+ * the rest of arch/x86/exit_car.S and calls main() itself instead of
+ * returning to _start. In main(), the TempRamExit FSP API is called
+ * to tear down the CAR and set up caching which can be overwritten
+ * after the API call. More info can be found in the Apollo Lake FSP
+ * Integration Guide included with the FSP binary. The below
+ * caching settings are based on an 8MiB Flash Size given as a
+ * parameter to TempRamInit.
+ *
+ * TempRamExit MTRR Settings:
+ * 0x00000000 - 0x0009FFFF | Write Back
+ * 0x000C0000 - Top of Low Memory | Write Back
+ * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect
+ * 0x100000000 - Top of High Memory | Write Back
+ */
+
+.text
+.global chipset_teardown_car
+chipset_teardown_car:
+
+ /* Set up new stack. */
+ mov post_car_stack_top, %esp
+
+ /* Call C code */
+ call main
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