[coreboot-gerrit] New patch to review for coreboot: amd/sb700/bootblock.c: Restore accidentally deleted code

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16384

-gerrit

commit 5f9f1384780d6d7b984a3b8a51c508560006fed9
Author: Martin Roth <martinroth at google.com>
Date:   Wed Aug 31 12:44:14 2016 -0600

    amd/sb700/bootblock.c: Restore accidentally deleted code
    
    The recent changes to this file from commit 6e5421d2
    (sb/amd/sb700: Add option to increase SPI speed to 33MHz)
    were accidentally removed in a code cleanup patch:
    commit ba28e8d7 (src/southbridge: Code formating).
    
    Change-Id: I6cf3e8f29d5c0384d35637f35e051be40318d20f
    Signed-off-by: Martin Roth <martinroth at google.com>
---
 src/southbridge/amd/sb700/Kconfig     | 10 ++++++++++
 src/southbridge/amd/sb700/bootblock.c | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
index 9a988a9..353c2a4 100644
--- a/src/southbridge/amd/sb700/Kconfig
+++ b/src/southbridge/amd/sb700/Kconfig
@@ -25,6 +25,16 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select HAVE_HARD_RESET
 	select SMBUS_HAS_AUX_CHANNELS
 
+config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
+	bool "Enable high speed SPI clock"
+	default n
+	help
+	  When set, the SPI clock will run at 33MHz instead
+	  of the compatibility mode 16.5MHz.  Note that not
+	  all ROMs are capable of 33MHz operation, so you
+	  will need to verify this option is appropriate for
+	  the ROM you are using.
+
 # Set for southbridge SP5100 which also uses SB700 driver
 config SOUTHBRIDGE_AMD_SUBTYPE_SP5100
 	bool
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index 97e749c..dfa4102 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -20,6 +20,10 @@
 
 #define IO_MEM_PORT_DECODE_ENABLE_5	0x48
 #define IO_MEM_PORT_DECODE_ENABLE_6	0x4a
+#define SPI_BASE_ADDRESS		0xa0
+
+#define SPI_CONTROL_1			0xc
+#define TEMPORARY_SPI_BASE_ADDRESS	0xfec10000
 
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
@@ -92,7 +96,37 @@ static void sb700_enable_rom(void)
 	pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
 }
 
+static void sb700_configure_rom(void)
+{
+	pci_devfn_t dev;
+	uint32_t dword;
+
+	dev = PCI_DEV(0, 0x14, 3);
+
+	if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) {
+		uint32_t prev_spi_cfg;
+		volatile uint32_t *spi_mmio;
+
+		/* Temporarily set up SPI access to change SPI speed */
+		prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS);
+		dword &= ~(0x7ffffff << 5);		/* SPI_BaseAddr */
+		dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5);
+		dword |= (0x1 << 1);			/* SpiRomEnable = 1 */
+		pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword);
+
+		spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1);
+		dword = *spi_mmio;
+		dword &= ~(0x3 << 12);	/* NormSpeed = 0x1 */
+		dword |= (0x1 << 12);
+		*spi_mmio = dword;
+
+		/* Restore previous SPI access */
+		pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg);
+	}
+}
+
 static void bootblock_southbridge_init(void)
 {
 	sb700_enable_rom();
+	sb700_configure_rom();
 }