[coreboot-gerrit] New patch to review for coreboot: mainboard/google/reef: add new memory SKUs
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Wed Aug 31 00:48:34 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16374
-gerrit
commit 01858a0a0e5f12c97903af282ba518db77d1229b
Author: Aaron Durbin <adurbin at chromium.org>
Date: Tue Aug 30 16:57:37 2016 -0500
mainboard/google/reef: add new memory SKUs
Two new SKUs are being utilized for reef DVT. Add the following:
Hynix 8GiB using H9HCNNNBPUMLHR-NLE -- id: 4'b0100
Hynix 4GIB using H9HCNNN8KUMLHR-NLE -- id: 4'b0101
BUG=chrome-os-partner:56738
Change-Id: I39ed9e827501939b92cbcce6092302b5a23d1d78
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/reef/romstage.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c
index e8d8e16..098fe31 100644
--- a/src/mainboard/google/reef/romstage.c
+++ b/src/mainboard/google/reef/romstage.c
@@ -111,6 +111,26 @@ static const struct lpddr4_sku skus[] = {
.ch1_rank_density = LP4_8Gb_DENSITY,
.part_num = "MT53B256M32D1NP",
},
+ /*
+ * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate the
+ * density as 8Gb per rank.
+ */
+ [4] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
+ .part_num = "H9HCNNNBPUMLHR",
+ },
+ /* H9HCNNN8KUMLHR-NLE - both logical channels */
+ [5] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "H9HCNNN8KUMLHR",
+ },
/* K4F8E304HB-MGCH - both logical channels */
[PROTO_SKU] = {
.speed = LP4_SPEED_2400,
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