[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3
Brandon Breitenstein (brandon.breitenstein@intel.com)
gerrit at coreboot.org
Tue Aug 30 01:47:12 CEST 2016
Brandon Breitenstein (brandon.breitenstein at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16352
-gerrit
commit 358b44de65fb9a5415a860a965477d20df9e3f57
Author: Brandon Breitenstein <brandon.breitenstein at intel.com>
Date: Mon Aug 29 16:24:24 2016 -0700
soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3
Updated FSP Header files to provide upd for periodic training
disable. This is for the SIC 1.1.3/150_11 FSP release. There
is a related patch submitted by Andrey to implement the
functionality of this UPD.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=built coreboot image with new headers
Change-Id: I2ba11aa3d2d664c1d34e39c4c8144fb1c4f2149a
Signed-off-by: Brandon Breitenstein <brandon.breitenstein at intel.com>
---
src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 35 +++++++++++++---------
src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 1 +
2 files changed, 22 insertions(+), 14 deletions(-)
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
index bb53497..994357c 100644
--- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
+++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
@@ -36,6 +36,7 @@ are permitted provided that the following conditions are met:
#include "FspUpd.h"
#include <fsp/upd.h>
+
#define MAX_CHANNELS_NUM 4
#define MAX_DIMMS_NUM 1
@@ -595,28 +596,28 @@ struct FSP_M_CONFIG {
**/
uint8_t RecoverDump;
-/** Offset 0x013A - Memory Region 0 Buffer Size
+/** Offset 0x013A - Memory Region 0 Buffer WrapAround
+ Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
+**/
+ uint8_t Msc0Wrap;
+
+/** Offset 0x013B - Memory Region 1 Buffer WrapAround
+ Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
+**/
+ uint8_t Msc1Wrap;
+
+/** Offset 0x013C - Memory Region 0 Buffer Size
Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
6-512MB, 7-1GB.
**/
uint32_t Msc0Size;
-/** Offset 0x013E - Memory Region 0 Buffer WrapAround
- Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
-**/
- uint8_t Msc0Wrap;
-
-/** Offset 0x013F - Memory Region 1 Buffer Size
+/** Offset 0x0140 - Memory Region 1 Buffer Size
Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
6-512MB, 7-1GB.
**/
uint32_t Msc1Size;
-/** Offset 0x0143 - Memory Region 1 Buffer WrapAround
- Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
-**/
- uint8_t Msc1Wrap;
-
/** Offset 0x0144 - PTI Mode
PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16.
**/
@@ -648,9 +649,15 @@ struct FSP_M_CONFIG {
**/
uint8_t SwTraceEn;
-/** Offset 0x014A
+/** Offset 0x014A - Periodic Retraining Disable
+ Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable.
+ $EN_DIS
+**/
+ uint8_t PeriodicRetrainingDisable;
+
+/** Offset 0x014B
**/
- uint8_t ReservedFspmUpd[6];
+ uint8_t ReservedFspmUpd[5];
} __attribute__((packed));
/** Fsp M Test Configuration
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
index 26f70a7..cb13f64 100644
--- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
+++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
@@ -36,6 +36,7 @@ are permitted provided that the following conditions are met:
#include "FspUpd.h"
#include <fsp/upd.h>
+
/** Fsp S Configuration
**/
struct FSP_S_CONFIG {
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