[coreboot-gerrit] New patch to review for coreboot: soc/intel/skylake: Use postcar functions for setting up new stack

[Rizwan Qureshi (rizwan.qureshi@intel.com)]

Rizwan Qureshi (rizwan.qureshi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16332

-gerrit

commit e234f4d2e3356df413abc676b8908b11b1563044
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Fri Aug 26 21:16:01 2016 +0530

    soc/intel/skylake: Use postcar functions for setting up new stack
    
    Setup stack and MTRRs using the postcar funtions provided
    in postcar_loader.c.
    
    Change-Id: Ia5771e70386dbae9fa181e3635021dd187345123
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
 src/soc/intel/skylake/romstage/romstage_fsp20.c | 50 +++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 3 deletions(-)

diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 57b2a52..95ae060 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -24,16 +24,25 @@
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <fsp/util.h>
+#include <fsp/memmap.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <timestamp.h>
 #include <vboot/vboot_common.h>
 
+/*
+ * Romstage needs some stack for decompressing ramstage images, since the lzma
+ * lib keeps its state on the stack during romstage.
+ */
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
 asmlinkage void *car_stage_c_entry(void)
 {
 	bool s3wake;
-	void *top_of_stack;
+	struct postcar_frame pcf;
+
+	uintptr_t top_of_ram;
 	struct chipset_power_state *ps;
 
 	console_init();
@@ -46,8 +55,43 @@ asmlinkage void *car_stage_c_entry(void)
 	s3wake = ps->prev_sleep_state == ACPI_S3;
 	fsp_memory_init(s3wake);
 
-	top_of_stack = setup_stack_and_mtrrs();
-	return top_of_stack;
+	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+		die("Unable to initialize postcar frame.\n");
+
+	/*
+	 * We need to make sure ramstage will be run cached. At this point exact
+	 * location of ramstage in cbmem is not known. Instruct postcar to cache
+	 * 16 megs under cbmem top which is a safe bet to cover ramstage.
+	 */
+	top_of_ram = (uintptr_t) cbmem_top();
+	printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+	/* cbmem_top() needs to be at least 16 MiB aligned */
+	assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
+
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
+
+	if(IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+		void *smm_base;
+		size_t smm_size;
+		uintptr_t tseg_base;
+
+		/*
+		 * Cache the TSEG region at the top of ram. This region is not
+		 * restricted to SMM mode until SMM has been relocated. By setting
+		 * the region to cacheable it provides faster access when relocating
+		 * the SMM handler as well as using the TSEG region for other purposes.
+		 */
+		smm_region(&smm_base, &smm_size);
+		tseg_base = (uintptr_t)smm_base;
+		postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+	}
+
+	/* Cache the ROM as WP just below 4GiB. */
+	postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1, 16*MiB, MTRR_TYPE_WRPROT);
+	postcar_commit_mtrrs(&pcf);
+
+	printk(BIOS_DEBUG, "top_of_stack = 0x%lx\n", pcf.stack);
+	return (void *)pcf.stack;
 }
 
 static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg)