[coreboot-gerrit] Patch set updated for coreboot: skylake/kunimitsu: Add initial FSP2.0 support
Rizwan Qureshi (rizwan.qureshi@intel.com)
gerrit at coreboot.org
Wed Aug 24 14:04:15 CEST 2016
Rizwan Qureshi (rizwan.qureshi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16267
-gerrit
commit 4030732e21b6f1b86cdd4349e411e5393e6227e0
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date: Thu Aug 11 21:56:40 2016 +0530
skylake/kunimitsu: Add initial FSP2.0 support
Add Initial pieces of code to support fsp2.0 in skylake and
kunimitsu, keeping the fsp1.1 flow intact.
Add Switches at relevant places to bisect the FSP1.1
and FSP2.0 paths to build and boot to romstage.
Consolidate header file inclusions in ramstage.h and romstage.h.
The relevant header files are included based on
CONFIG_PLATFORM_USES_FSP1_1 or CONFIG_PLATFORM_USES_FSP2_0 configs.
Add the below files,
car_stage.S:
Add romstage entry point (car_stage_entry).
This calls into romstage_fsp20.c and aslo handles
the car teardown.
romstage_fsp20.c:
Call fsp_memory_init() and also has the callback
for filling memory init parameters.
stage_cache.c:
Provides a region range within SMM area for use in stage
caching.
This function is present in FSP1.1, copied here for
use when using FSP2.0.
memmap.h
Includes prototypes for mmap_region_granularity and smm related
funtions.
This header is part of FSP1.1, copied here for use
for FSP2.0
The build was complaining about smaller Bootblock, hence increase the
size of bootblock by 4K i.e., set CONFIG_C_ENV_BOOTBLOCK_SIZE
to 0x9000 (36K).
Also add monotonic_timer.c to verstage.
TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0
Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
src/mainboard/intel/kunimitsu/Makefile.inc | 5 +
src/mainboard/intel/kunimitsu/ramstage.c | 8 +-
src/mainboard/intel/kunimitsu/romstage_fsp20.c | 20 ++++
src/soc/intel/skylake/Kconfig | 3 +-
src/soc/intel/skylake/Makefile.inc | 13 ++-
src/soc/intel/skylake/chip_fsp20.c | 29 +++++
src/soc/intel/skylake/igd.c | 3 +-
src/soc/intel/skylake/include/soc/memmap.h | 47 ++++++++
src/soc/intel/skylake/include/soc/ramstage.h | 16 +++
src/soc/intel/skylake/include/soc/romstage.h | 16 ++-
src/soc/intel/skylake/include/soc/smm.h | 3 +-
src/soc/intel/skylake/include/soc/vr_config.h | 13 ++-
src/soc/intel/skylake/memmap.c | 1 -
src/soc/intel/skylake/reset.c | 31 +++++
src/soc/intel/skylake/romstage/Makefile.inc | 5 +-
src/soc/intel/skylake/romstage/car_stage.S | 143 ++++++++++++++++++++++++
src/soc/intel/skylake/romstage/romstage_fsp20.c | 37 ++++++
src/soc/intel/skylake/stage_cache.c | 28 +++++
src/soc/intel/skylake/vr_config.c | 10 +-
19 files changed, 415 insertions(+), 16 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc
index cafa12c..3f58061 100644
--- a/src/mainboard/intel/kunimitsu/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/Makefile.inc
@@ -34,3 +34,8 @@ ramstage-y += pei_data.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
+romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs))
+endif
+
diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c
index 563c715..5c67d34 100644
--- a/src/mainboard/intel/kunimitsu/ramstage.c
+++ b/src/mainboard/intel/kunimitsu/ramstage.c
@@ -16,7 +16,13 @@
#include <soc/ramstage.h>
#include "gpio.h"
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+void mainboard_silicon_init_params(
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+ SILICON_INIT_UPD *params
+#else
+ struct FSP_S_CONFIG *params
+#endif
+)
{
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */
diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
new file mode 100644
index 0000000..5c27270
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(struct FSPM_UPD *mupd)
+{
+}
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 7fa129b..840aded 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
select RTC
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select SOC_INTEL_COMMON_GFX_OPREGION if PLATFORM_USES_FSP2_0
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
@@ -99,7 +100,7 @@ config DCACHE_BSP_STACK_SIZE
config C_ENV_BOOTBLOCK_SIZE
hex
- default 0x8000
+ default 0x9000
config EXCLUDE_NATIVE_SD_INTERFACE
bool
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index b92eab3..466b791 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -28,6 +28,7 @@ bootblock-y += pmutil.c
bootblock-y += tsc_freq.c
verstage-y += flash_controller.c
+verstage-y += monotonic_timer.c
verstage-y += pch.c
verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
@@ -39,12 +40,15 @@ romstage-y += pch.c
romstage-y += pcr.c
romstage-y += pei_data.c
romstage-y += pmutil.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += stage_cache.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
romstage-y += smbus_common.c
romstage-y += tsc_freq.c
romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
-ramstage-y += chip.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c
ramstage-y += cpu.c
ramstage-y += cpu_info.c
ramstage-y += dsp.c
@@ -64,7 +68,9 @@ ramstage-y += pcr.c
ramstage-y += pei_data.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-y += ramstage.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += stage_cache.c
ramstage-y += sd.c
ramstage-y += smbus.c
ramstage-y += smbus_common.c
@@ -92,7 +98,12 @@ smm-$(CONFIG_UART_DEBUG) += uart_debug.c
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
+else
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake
+endif
# Currently used for microcode path.
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
new file mode 100644
index 0000000..4ea0623
--- /dev/null
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <chip.h>
+#include <bootstate.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd)
+{
+}
+
+struct pci_operations soc_pci_ops = {
+};
+
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index 3e29ab0..027e1dc 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -24,7 +24,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <drivers/intel/gma/i915_reg.h>
-#include <fsp/gop.h>
#include <soc/acpi.h>
#include <soc/cpu.h>
#include <soc/pm.h>
@@ -117,6 +116,7 @@ static void igd_init(struct device *dev)
}
/* Initialize IGD OpRegion, called from ACPI code */
+#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION)
static int init_igd_opregion(igd_opregion_t *opregion)
{
const optionrom_vbt_t *vbt;
@@ -172,6 +172,7 @@ static int init_igd_opregion(igd_opregion_t *opregion)
return 0;
}
+#endif
static unsigned long write_acpi_igd_opregion(device_t device,
unsigned long current, struct acpi_rsdp *rsdp)
diff --git a/src/soc/intel/skylake/include/soc/memmap.h b/src/soc/intel/skylake/include/soc/memmap.h
new file mode 100644
index 0000000..965bce6
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/memmap.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _COMMON_MEMMAP_H_
+#define _COMMON_MEMMAP_H_
+
+#include <types.h>
+
+/*
+ * mmap_region_granularity must to return a size which is a positive non-zero
+ * integer multiple of the SMM size when SMM is in use. When not using SMM,
+ * this value should be set to 8 MiB.
+ */
+size_t mmap_region_granularity(void);
+
+/* Fills in the arguments for the entire SMM region covered by chipset
+ * protections. e.g. TSEG. */
+void smm_region(void **start, size_t *size);
+
+enum {
+ /* SMM handler area. */
+ SMM_SUBREGION_HANDLER,
+ /* SMM cache region. */
+ SMM_SUBREGION_CACHE,
+ /* Chipset specific area. */
+ SMM_SUBREGION_CHIPSET,
+ /* Total sub regions supported. */
+ SMM_SUBREGION_NUM,
+};
+
+/* Fills in the start and size for the requested SMM subregion. Returns
+ * 0 on susccess, < 0 on failure. */
+int smm_subregion(int sub, void **start, size_t *size);
+
+#endif /* _COMMON_MEMMAP_H_ */
diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h
index 55f9972..356df89 100644
--- a/src/soc/intel/skylake/include/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/soc/ramstage.h
@@ -19,7 +19,23 @@
#include <chip.h>
#include <device/device.h>
+
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+
+#include <fsp/gop.h>
#include <fsp/ramstage.h>
+#include <fsp/soc_binding.h>
+
+#else /* FSP2.0 */
+
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <soc/intel/common/opregion.h>
+
+void intel_silicon_init(void);
+void mainboard_silicon_init_params(struct FSP_S_CONFIG *params);
+
+#endif
void pch_enable_dev(device_t dev);
void soc_init_pre_device(void *chip_info);
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index 6c40bd6..6939378 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -17,13 +17,23 @@
#ifndef _SOC_ROMSTAGE_H_
#define _SOC_ROMSTAGE_H_
+#include <arch/cpu.h>
+#include <soc/pei_data.h>
+
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+
#include <fsp/romstage.h>
+#else /* FSP 2.0 */
+
+#include <fsp/api.h>
+
+asmlinkage void *car_stage_c_entry(void);
+void mainboard_memory_init_params(struct FSPM_UPD *mupd);
+#endif
+
void systemagent_early_init(void);
-void intel_early_me_status(void);
-void enable_smbus(void);
int smbus_read_byte(unsigned device, unsigned address);
-
int early_spi_read_wpsr(u8 *sr);
void mainboard_fill_spd_data(struct pei_data *pei_data);
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index fa8da46..af4821f 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -19,8 +19,7 @@
#include <stdint.h>
#include <cpu/x86/msr.h>
-#include <fsp/memmap.h>
-#include <fsp/romstage.h>
+#include <soc/memmap.h>
#include <soc/gpio.h>
struct ied_header {
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h
index d70fd21..9516daf 100644
--- a/src/soc/intel/skylake/include/soc/vr_config.h
+++ b/src/soc/intel/skylake/include/soc/vr_config.h
@@ -19,7 +19,11 @@
#ifndef _SOC_VR_CONFIG_H_
#define _SOC_VR_CONFIG_H_
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
#include <fsp/soc_binding.h>
+#else
+#include <fsp/api.h>
+#endif
struct vr_config {
@@ -74,7 +78,12 @@ enum vr_domain{
NUM_VR_DOMAINS
};
-void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
- const struct vr_config *cfg);
+void fill_vr_domain_config(
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+ SILICON_INIT_UPD *params,
+#else
+ struct FSP_S_CONFIG *params,
+#endif
+ int domain, const struct vr_config *cfg);
#endif
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 6af1371..96debfd 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -21,7 +21,6 @@
#include <device/pci.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/systemagent.h>
#include <stdlib.h>
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
new file mode 100644
index 0000000..25a41c2
--- /dev/null
+++ b/src/soc/intel/skylake/reset.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <reset.h>
+
+void chipset_handle_reset(enum fsp_status status)
+{
+ switch(status) {
+ case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
+ printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
+ break;
+ default:
+ printk(BIOS_ERR, "unhandled reset type %x\n", status);
+ die("unknown reset type");
+ break;
+ }
+}
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 31a452f..e552c39 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,7 +1,8 @@
-
verstage-y += power_state.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage.S
romstage-y += power_state.c
-romstage-y += romstage.c
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
romstage-y += spi.c
romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S
new file mode 100644
index 0000000..dc4259c
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/car_stage.S
@@ -0,0 +1,143 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <rules.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+.section ".text"
+.global car_stage_entry
+
+car_stage_entry:
+
+ /* Enter the C code */
+ call car_stage_c_entry
+
+/*
+ * Car teardown
+ */
+ /*
+ * eax: New stack address
+ */
+
+ /* Switch to the stack in RAM */
+ movl %eax, %esp
+
+ #include <soc/car_teardown.S>
+
+ /* Display the MTRRs */
+ call soc_display_mtrrs
+
+ /*
+ * The stack contents are initialized in src/soc/intel/common/stack.c
+ * to be the following:
+ *
+ * *
+ * *
+ * *
+ * +36: MTRR mask 1 63:32
+ * +32: MTRR mask 1 31:0
+ * +28: MTRR base 1 63:32
+ * +24: MTRR base 1 31:0
+ * +20: MTRR mask 0 63:32
+ * +16: MTRR mask 0 31:0
+ * +12: MTRR base 0 63:32
+ * +8: MTRR base 0 31:0
+ * +4: Number of MTRRs to setup (described above)
+ * +0: Number of variable MTRRs to clear
+ */
+
+#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
+ push %esp
+ call soc_set_mtrrs
+
+ /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */
+ movl %eax, %esp
+#else
+ /* Clear all of the variable MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+ clr %eax
+ clr %edx
+
+1:
+ testl %ebx, %ebx
+ jz 1f
+ wrmsr /* Write MTRR base. */
+ inc %ecx
+ wrmsr /* Write MTRR mask. */
+ inc %ecx
+ dec %ebx
+ jmp 1b
+
+1:
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+2:
+ testl %ebx, %ebx
+ jz 2f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
+ wrmsr
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
+ wrmsr
+ inc %ecx
+
+ dec %ebx
+ jmp 2b
+2:
+#endif /* CONFIG_SOC_SETS_MSRS */
+
+ post_code(0x39)
+
+ /* And enable cache again after setting MTRRs. */
+ movl %cr0, %eax
+ andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+ movl %eax, %cr0
+
+ post_code(0x3a)
+
+#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
+ call soc_enable_mtrrs
+#else
+ /* Enable MTRR. */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ rdmsr
+ orl $MTRR_DEF_TYPE_EN, %eax
+ wrmsr
+#endif /* CONFIG_SOC_SETS_MSRS */
+
+ post_code(0x3b)
+
+ /* Invalidate the cache again. */
+ invd
+
+__main:
+ post_code(POST_PREPARE_RAMSTAGE)
+ cld /* Clear direction flag. */
+
+ call copy_and_run
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
new file mode 100644
index 0000000..e56eb35
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/romstage.h>
+
+asmlinkage void *car_stage_c_entry(void)
+{
+ bool s3wake = false;
+ console_init();
+ fsp_memory_init(s3wake);
+ return NULL;
+}
+static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg)
+{
+}
+
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){
+
+ struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+ soc_memory_init_params(m_cfg);
+ mainboard_memory_init_params(mupd);
+}
diff --git a/src/soc/intel/skylake/stage_cache.c b/src/soc/intel/skylake/stage_cache.c
new file mode 100644
index 0000000..98bd174
--- /dev/null
+++ b/src/soc/intel/skylake/stage_cache.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <soc/memmap.h>
+#include <stage_cache.h>
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+ if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
+ printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
+ *base = NULL;
+ *size = 0;
+ }
+}
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 40223e3..db0805e 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -15,6 +15,7 @@
*/
#include <soc/vr_config.h>
+#include <fsp/api.h>
/* Default values for domain configuration. PSI3 and PSI4 are disabled. */
static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
@@ -80,8 +81,13 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
},
};
-void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
- const struct vr_config *chip_cfg)
+void fill_vr_domain_config(
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+ SILICON_INIT_UPD *params,
+#else
+ struct FSP_S_CONFIG *params,
+#endif
+ int domain, const struct vr_config *chip_cfg)
{
const struct vr_config *cfg;
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