[coreboot-gerrit] Patch set updated for coreboot: arch/riscv: Enable U-mode/S-mode counters (stime, etc.)
Jonathan Neuschäfer (j.neuschaefer@gmx.net)
gerrit at coreboot.org
Mon Aug 22 20:16:03 CEST 2016
Jonathan Neuschäfer (j.neuschaefer at gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16262
-gerrit
commit 05b769af2909cefa9563fa7942284f67dcec756b
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date: Mon Aug 22 19:37:15 2016 +0200
arch/riscv: Enable U-mode/S-mode counters (stime, etc.)
Change-Id: Ie62f60b2e237fa4921384e3894569ae29639f563
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
src/arch/riscv/virtual_memory.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 98b7edc..fab7d90 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -218,4 +218,8 @@ void mstatus_init(void)
| (1 << CAUSE_FAULT_STORE)
| (1 << CAUSE_USER_ECALL)
);
+
+ /* Enable all user/supervisor-mode counters */
+ write_csr(mscounteren, 0b111);
+ write_csr(mucounteren, 0b111);
}
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