[coreboot-gerrit] New patch to review for coreboot: [WIP] src: replace device_t type with pnp/pci_defn_t
Antonello Dettori (dev@dettori.io)
gerrit at coreboot.org
Mon Aug 22 16:38:42 CEST 2016
Antonello Dettori (dev at dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16293
-gerrit
commit 1f44343b0caa818c31e8952d9fc318053cd5b7dd
Author: Antonello Dettori <dev at dettori.io>
Date: Sun Aug 21 18:26:05 2016 +0200
[WIP] src: replace device_t type with pnp/pci_defn_t
Replace device_t type with pnp/pci_defn_t.
Change-Id: Iec2d14a5afd85c5268601c72ed31f9311dfe1982
Signed-off-by: Antonello Dettori <dev at dettori.io>
---
src/device/pci_early.c | 6 +++---
src/drivers/net/ne2k.c | 2 +-
src/include/device/pci.h | 6 +++---
src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +-
src/mainboard/asus/a8v-e_se/romstage.c | 2 +-
src/mainboard/asus/f2a85-m/romstage.c | 2 +-
src/mainboard/asus/k8v-x/romstage.c | 2 +-
src/mainboard/asus/kfsn4-dre/romstage.c | 4 ++--
src/mainboard/asus/kfsn4-dre_k8/romstage.c | 4 ++--
src/mainboard/asus/m2n-e/romstage.c | 2 +-
src/mainboard/asus/m2v-mx_se/romstage.c | 2 +-
src/mainboard/asus/m2v/romstage.c | 4 ++--
src/mainboard/bcom/winnetp680/romstage.c | 2 +-
src/mainboard/biostar/am1ml/romstage.c | 2 +-
src/mainboard/getac/p470/romstage.c | 8 ++++----
src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 2 +-
src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 2 +-
src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 2 +-
src/mainboard/ibase/mb899/romstage.c | 2 +-
src/mainboard/iei/pm-lx2-800-r10/romstage.c | 2 +-
src/mainboard/intel/cougar_canyon2/romstage.c | 2 +-
src/mainboard/intel/d510mo/romstage.c | 2 +-
src/mainboard/intel/emeraldlake2/romstage.c | 2 +-
src/mainboard/jetway/j7f2/romstage.c | 2 +-
src/mainboard/kontron/986lcd-m/romstage.c | 6 +++---
src/mainboard/kontron/ktqm77/romstage.c | 6 +++---
src/mainboard/lenovo/t60/romstage.c | 2 +-
src/mainboard/lenovo/x60/romstage.c | 2 +-
src/mainboard/roda/rk886ex/romstage.c | 8 ++++----
src/mainboard/roda/rk9/romstage.c | 2 +-
src/mainboard/supermicro/h8qme_fam10/romstage.c | 4 ++--
src/mainboard/tyan/s8226/romstage.c | 2 +-
src/mainboard/via/epia-cn/romstage.c | 2 +-
src/mainboard/via/epia-m700/romstage.c | 8 ++++----
src/mainboard/via/vt8454c/romstage.c | 2 +-
src/northbridge/amd/amdfam10/early_ht.c | 2 +-
src/northbridge/amd/amdk8/early_ht.c | 4 ++--
src/northbridge/amd/lx/northbridge.h | 1 -
src/northbridge/intel/e7505/debug.c | 6 +++---
src/northbridge/intel/e7505/raminit.h | 2 +-
src/northbridge/intel/fsp_rangeley/northbridge.h | 2 +-
src/northbridge/intel/fsp_rangeley/port_access.c | 4 +---
src/northbridge/intel/i945/debug.c | 4 ++--
src/northbridge/intel/nehalem/acpi.c | 2 +-
src/soc/intel/apollolake/spi.c | 2 +-
src/soc/intel/broadwell/romstage/pch.c | 2 +-
src/soc/intel/broadwell/romstage/uart.c | 2 +-
src/soc/intel/skylake/romstage/pch.c | 2 +-
src/soc/intel/skylake/romstage/romstage.c | 2 +-
src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++--
src/southbridge/amd/cimx/sb700/early.c | 6 +++---
src/southbridge/amd/cimx/sb800/early.c | 2 +-
src/southbridge/amd/pi/hudson/early_setup.c | 6 +++---
src/southbridge/intel/fsp_i89xx/romstage.c | 2 +-
src/southbridge/intel/fsp_rangeley/early_smbus.c | 2 +-
src/southbridge/intel/fsp_rangeley/early_usb.c | 2 +-
src/southbridge/intel/i82371eb/early_pm.c | 2 +-
src/southbridge/intel/i82371eb/early_smbus.c | 2 +-
src/southbridge/intel/i82801dx/early_smbus.c | 2 +-
src/southbridge/intel/i82801dx/i82801dx.h | 2 +-
src/southbridge/intel/i82801dx/smihandler.c | 2 +-
src/southbridge/intel/i82801gx/early_smbus.c | 2 +-
src/southbridge/intel/i82801gx/i82801gx.h | 5 ++++-
63 files changed, 95 insertions(+), 95 deletions(-)
diff --git a/src/device/pci_early.c b/src/device/pci_early.c
index 7107738..611b31b 100644
--- a/src/device/pci_early.c
+++ b/src/device/pci_early.c
@@ -73,7 +73,7 @@ unsigned pci_find_capability(pci_devfn_t dev, unsigned cap)
#if CONFIG_EARLY_PCI_BRIDGE
-static void pci_bridge_reset_secondary(device_t p2p_bridge)
+static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge)
{
u16 reg16;
@@ -90,7 +90,7 @@ static void pci_bridge_reset_secondary(device_t p2p_bridge)
pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
}
-static void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary)
+static void pci_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary)
{
/* Disable config transaction forwarding. */
pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
@@ -100,7 +100,7 @@ static void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary)
pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
}
-static void pci_bridge_set_mmio(device_t p2p_bridge, u32 base, u32 size)
+static void pci_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size)
{
u16 reg16;
diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c
index b59fe08..0b16bf0 100644
--- a/src/drivers/net/ne2k.c
+++ b/src/drivers/net/ne2k.c
@@ -394,7 +394,7 @@ static void ns8390_reset(unsigned int eth_nic_base)
int ne2k_init(unsigned int eth_nic_base) {
- device_t dev;
+ pci_devfn_t dev;
unsigned char c;
/* Power management controller */
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 9ef3614..e167752 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -108,13 +108,13 @@ static inline const struct pci_operations *ops_pci(device_t dev)
#endif /* ! __SIMPLE_DEVICE__ */
-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last);
unsigned pci_find_capability(pci_devfn_t dev, unsigned cap);
-#else /* !__PRE_RAM__ */
+#else /* !__SIMPLE_DEVICE__ */
unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last);
unsigned pci_find_capability(device_t dev, unsigned cap);
-#endif /* __PRE_RAM__ */
+#endif /* __SIMPLE_DEVICE__ */
void pci_early_bridge_init(void);
int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base);
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 30a1a2a..e6b8ef5 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -84,7 +84,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 4d965e7..4a33f77 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -84,7 +84,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 709dbcd..0e502e7 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -62,7 +62,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
hudson_pci_port80();
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 14d529c..0f98062 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -82,7 +82,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index 05ba1f9..0889f24 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -82,7 +82,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
*/
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus);
@@ -133,7 +133,7 @@ static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit
for (i = 0; i < 4; i++) {
u32 id;
- device_t dev;
+ pci_devfn_t dev;
if (i == 0) /* SB chain */
dev = PCI_DEV(i * 0x40, bus_unit_id, 0);
else
diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
index fe83ca8..b547461 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
@@ -80,7 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
*/
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus);
@@ -131,7 +131,7 @@ static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit
for (i = 0; i < 4; i++) {
u32 id;
- device_t dev;
+ pci_devfn_t dev;
if (i == 0) /* SB chain */
dev = PCI_DEV(i * 0x40, bus_unit_id, 0);
else
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index f9e5d46..3bf54db 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -76,7 +76,7 @@ static void sio_setup(void)
{
u8 byte;
u32 dword;
- device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
+ pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
/* Subject decoding */
byte = pci_read_config8(dev, 0x7b);
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 544873c..daf0b50 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -101,7 +101,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index bceecf8..9eacecf 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -85,7 +85,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
@@ -183,7 +183,7 @@ static void m2v_it8712f_gpio_init(void)
static void m2v_bus_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
printk(BIOS_SPEW, "m2v_bus_init\n");
diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c
index f2144ff..0a3ba72 100644
--- a/src/mainboard/bcom/winnetp680/romstage.c
+++ b/src/mainboard/bcom/winnetp680/romstage.c
@@ -42,7 +42,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index 12d9eee..d7da2bb 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -110,7 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val, t32;
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
u32 *addr32;
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 396a2ec..0447019 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -103,19 +103,19 @@ static void ich7_enable_lpc(void)
* the two. Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method.
*/
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0x55, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0xaa, port);
}
-static void pnp_write_register(device_t dev, int reg, int val)
+static void pnp_write_register(pnp_devfn_t dev, int reg, int val)
{
unsigned int port = dev >> 8;
outb(reg, port);
@@ -124,7 +124,7 @@ static void pnp_write_register(device_t dev, int reg, int val)
static void early_superio_config(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev=PNP_DEV(0x4e, 0x00);
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index be6043a..dd889d1 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -33,7 +33,7 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
-static void it8728f_b75md3h_disable_reboot(device_t dev)
+static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev)
{
/* GPIO SIO settings */
ite_reg_write(dev, 0xEF, 0x7E); // magic
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index 55a2a96..fcdac6d 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -33,7 +33,7 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
-static void it8728f_b75md3v_disable_reboot(device_t dev)
+static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev)
{
/* GPIO SIO settings */
ite_reg_write(dev, 0xEF, 0x7E); // magic
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index b6be8fb..2503db9 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -41,7 +41,7 @@
static void mb_gpio_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
/* Southbridge GPIOs. */
dev = PCI_DEV(0x0, 0x1f, 0x0);
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 9d2b90a..4496922 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -74,7 +74,7 @@ static void ich7_enable_lpc(void)
*/
static void early_superio_config_w83627ehg(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev = DUMMY_DEV;
pnp_enter_ext_func_mode(dev);
diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c
index 9abeaf9..d35e9e7 100644
--- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c
+++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c
@@ -64,7 +64,7 @@ void main(unsigned long bist)
console_init();
/* Enable COM3. */
- device_t dev = PNP_DEV(0x2e, 0x0b);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 0x0b);
u16 port = dev >> 8;
outb(0x55, port);
pnp_set_logical_device(dev);
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 998528d..ae1b36c 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -51,7 +51,7 @@ static inline void reset_system(void)
static void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index f73bf64..bf390c9 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -38,7 +38,7 @@
/* Early mainboard specific GPIO setup */
static void mb_gpio_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
/* Southbridge GPIOs. */
dev = PCI_DEV(0x0, 0x1f, 0x0);
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 069b6ad..aa0eadc 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -41,7 +41,7 @@
void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c
index 0de239c..d479072 100644
--- a/src/mainboard/jetway/j7f2/romstage.c
+++ b/src/mainboard/jetway/j7f2/romstage.c
@@ -46,7 +46,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 3dcf4cc..d2f6684 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -76,14 +76,14 @@ static void ich7_enable_lpc(void)
}
/* TODO: superio code should really not be in mainboard */
-static void pnp_enter_func_mode(device_t dev)
+static void pnp_enter_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
-static void pnp_exit_func_mode(device_t dev)
+static void pnp_exit_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
@@ -96,7 +96,7 @@ static void pnp_exit_func_mode(device_t dev)
*/
static void early_superio_config_w83627thg(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev=PNP_DEV(0x2e, W83627THG_SP1);
pnp_enter_func_mode(dev);
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 973119b..ade2a78 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -63,14 +63,14 @@ void rcba_config(void)
RCBA32(FD) = reg32;
}
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
@@ -80,7 +80,7 @@ void mainboard_config_superio(void)
{
int lvds_3v = 0; // 0 (5V) or 1 (3V3)
int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled
- device_t dev = PNP_DEV(0x2e, 0x9);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 0x9);
pnp_enter_ext_func_mode(dev);
pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */
pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 3ed6afd..d3cd90c 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -95,7 +95,7 @@ static void ich7_enable_lpc(void)
static void early_superio_config(void)
{
int timeout = 100000;
- device_t dev = PNP_DEV(0x2e, 3);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 3);
pnp_write_config(dev, 0x29, 0xa0);
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index aabbf65..c735ce2 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -102,7 +102,7 @@ static void ich7_enable_lpc(void)
static void early_superio_config(void)
{
int timeout = 100000;
- device_t dev = PNP_DEV(0x2e, 3);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 3);
pnp_write_config(dev, 0x29, 0x06);
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index f3af5fa..bdb2051 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -90,19 +90,19 @@ static void ich7_enable_lpc(void)
* the two. Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method.
*/
-static inline void pnp_enter_ext_func_mode(device_t dev)
+static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0x55, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0xaa, port);
}
-static void pnp_write_register(device_t dev, int reg, int val)
+static void pnp_write_register(pnp_devfn_t dev, int reg, int val)
{
unsigned int port = dev >> 8;
outb(reg, port);
@@ -111,7 +111,7 @@ static void pnp_write_register(device_t dev, int reg, int val)
static void early_superio_config(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev=PNP_DEV(0x2e, 0x00);
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index fc0c8d3..9ed71b7 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -84,7 +84,7 @@ static void default_superio_gpio_setup(void)
GP1 GP2 GP3 GP4
fd 17 88 14
*/
- const device_t sio = PNP_DEV(0x2e, 0);
+ const pnp_devfn_t sio = PNP_DEV(0x2e, 0);
/* Enter super-io's configuration state. */
pnp_enter_conf_state(sio);
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 4661f45..c9178b8 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -113,14 +113,14 @@ static const u8 spd_addr[] = {
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
/* TODO: superio code should really not be in mainboard */
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index ea877b7..7460f20 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -43,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x31);
/* For serial port. */
- device_t dev = PCI_DEV(0, 0x14, 3);
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index a28bf78..71f00c9 100644
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -39,7 +39,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 83af426..26ee24f 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -50,7 +50,7 @@
*/
static int acpi_is_wakeup_early_via_vx800(void)
{
- device_t dev;
+ pci_devfn_t dev;
u16 tmp, result;
printk(BIOS_DEBUG, "In acpi_is_wakeup_early_via_vx800\n");
@@ -76,7 +76,7 @@ static int acpi_is_wakeup_early_via_vx800(void)
/* All content of this function came from the cx700 port of coreboot. */
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
#if 0
/*
* Add and close this switch, since some line cause error, some
@@ -370,8 +370,8 @@ void main(unsigned long bist)
{
u16 boot_mode;
u8 rambits, Data8, Data;
- device_t device;
- /* device_t dev; */
+ pci_devfn_t device;
+ /* pci_devfn_t dev; */
/*
* Enable multifunction for northbridge. These 4 lines (until
diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c
index d2af46c..114494b 100644
--- a/src/mainboard/via/vt8454c/romstage.c
+++ b/src/mainboard/via/vt8454c/romstage.c
@@ -33,7 +33,7 @@
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0);
if (dev == PCI_DEV_INVALID) {
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index 3e59a32..d292eb9 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -93,7 +93,7 @@ static void enumerate_ht_chain(void)
if ((flags >> 13) == 0) {
unsigned count;
unsigned ctrl, ctrl_off;
- device_t devx;
+ pci_devfn_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if(next_unitid>=0x18) {
diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index 1bc34e4..eb91371 100644
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -13,7 +13,7 @@ static void enumerate_ht_chain(void)
* links needs to be programed to point at bus 0.
*/
unsigned next_unitid, last_unitid;
- device_t dev;
+ pci_devfn_t dev;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
//let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
unsigned real_last_unitid = 0;
@@ -61,7 +61,7 @@ static void enumerate_ht_chain(void)
if ((flags >> 13) == 0) {
unsigned count;
unsigned ctrl, ctrl_off;
- device_t devx;
+ pci_devfn_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if(next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f.
diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h
index 1e0e650..9a4ff29 100644
--- a/src/northbridge/amd/lx/northbridge.h
+++ b/src/northbridge/amd/lx/northbridge.h
@@ -19,7 +19,6 @@
#include <cpu/amd/lxdef.h>
/* northbridge.c */
-unsigned int lx_scan_root_bus(device_t root, unsigned int max);
int sizeram(void);
/* northbridgeinit.c */
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index cdf6e7e..cef0f3a 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -21,7 +21,7 @@ void print_debug_pci_dev(unsigned dev)
void print_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
@@ -54,7 +54,7 @@ void dump_pci_device(unsigned dev)
void dump_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
@@ -71,7 +71,7 @@ void dump_pci_devices(void)
void dump_pci_devices_on_bus(unsigned busn)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(busn, 0, 0);
dev <= PCI_DEV(busn, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h
index 8eb4990..979ae0a 100644
--- a/src/northbridge/intel/e7505/raminit.h
+++ b/src/northbridge/intel/e7505/raminit.h
@@ -6,7 +6,7 @@
#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)
struct mem_controller {
- device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller
+ pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller
// SMBus addresses of DIMM slots for each channel,
// in order from closest to MCH to furthest away
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h
index 61931fd..db219c5 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.h
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.h
@@ -72,7 +72,7 @@ void dump_spd_registers(void);
void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
void northbridge_acpi_fill_ssdt_generator(device_t device);
#endif
diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c
index c4730a9..1ec423e 100644
--- a/src/northbridge/intel/fsp_rangeley/port_access.c
+++ b/src/northbridge/intel/fsp_rangeley/port_access.c
@@ -14,9 +14,7 @@
* GNU General Public License for more details.
*/
-#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
-#endif
+#define __SIMPLE_DEVICE__ // Use simple device model even in ramstage
#include <stdint.h>
#include <arch/io.h>
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index d26e84e..65189bd 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -23,7 +23,7 @@
void print_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
@@ -61,7 +61,7 @@ void dump_pci_device(unsigned dev)
void dump_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
index 42761fa..3471282 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -130,7 +130,7 @@ static int init_opregion_vbt(igd_opregion_t * opregion)
/* Initialize IGD OpRegion, called from ACPI code */
int init_igd_opregion(igd_opregion_t * opregion)
{
- device_t igd;
+ pci_devfn_t igd;
u16 reg16;
memset((void *)opregion, 0, sizeof(igd_opregion_t));
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c
index 7b390bb..ae8c7a7 100644
--- a/src/soc/intel/apollolake/spi.c
+++ b/src/soc/intel/apollolake/spi.c
@@ -47,7 +47,7 @@ enum errors {
/* Reduce data-passing burden by grouping transaction data in a context. */
struct spi_ctx {
uintptr_t mmio_base;
- device_t pci_dev;
+ pci_devfn_t pci_dev;
uint32_t hsfsts_on_last_error;
};
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index 74d3125..03a9f9b 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -131,7 +131,7 @@ static void pch_enable_lpc(void)
pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec);
}
-static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
+static void pcie_update_cfg(pci_devfn_t dev, int reg, u32 mask, u32 or)
{
u32 reg32;
diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c
index 1ea7cc2..ed03418 100644
--- a/src/soc/intel/broadwell/romstage/uart.c
+++ b/src/soc/intel/broadwell/romstage/uart.c
@@ -48,7 +48,7 @@ void pch_uart_init(void)
{
/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
u32 gpiodf = 0x131f;
- device_t dev;
+ pci_devfn_t dev;
/* Put UART in byte access mode for 16550 compatibility */
switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {
diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c
index 26677e8..47d0020 100644
--- a/src/soc/intel/skylake/romstage/pch.c
+++ b/src/soc/intel/skylake/romstage/pch.c
@@ -81,7 +81,7 @@ static void pch_enable_lpc(void)
static void pch_device_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
u32 reg32;
u16 tcobase;
u16 tcocnt;
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 56a5a92..9aa1457 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -241,7 +241,7 @@ void soc_after_ram_init(struct romstage_params *params)
* init and MRC cache is saved.
*/
u32 disb_val = 0;
- device_t dev = PCH_DEV_PMC;
+ pci_devfn_t dev = PCH_DEV_PMC;
disb_val = pci_read_config32(dev, GEN_PMCON_A);
disb_val |= DISB;
/* Preserve bits which get cleared up if written 1 */
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index 57119f9..1cdaa05 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -28,7 +28,7 @@
void hudson_pci_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
/* P2P Bridge */
dev = PCI_DEV(0, 0x14, 4);
@@ -73,7 +73,7 @@ void hudson_pci_port80(void)
void hudson_lpc_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
/* Enable LPC controller */
outb(0xEC, 0xCD6);
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 5af2a5e..d706a56 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -30,7 +30,7 @@
*/
u32 get_sbdn(u32 bus)
{
- device_t dev;
+ pci_devfn_t dev;
printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__);
dev = pci_locate_device_on_bus(
@@ -65,7 +65,7 @@ void sb_Poweron_Init(void)
void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
{
/* TODO: Now assume wio_index=0 */
- device_t dev;
+ pci_devfn_t dev;
u8 reg8;
//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
@@ -79,7 +79,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
void sb7xx_51xx_disable_wideio(u8 wio_index)
{
/* TODO: Now assume wio_index=0 */
- device_t dev;
+ pci_devfn_t dev;
u8 reg8;
//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 2a10c0e..c6d8393 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -28,7 +28,7 @@
*/
u32 get_sbdn(u32 bus)
{
- device_t dev;
+ pci_devfn_t dev;
printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__);
//dev = PCI_DEV(bus, 0x14, 0);
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index f4fcf8b..dce1620 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -60,7 +60,7 @@ void configure_hudson_uart(void)
void hudson_pci_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
/* P2P Bridge */
dev = PCI_DEV(0, 0x14, 4);
@@ -105,7 +105,7 @@ void hudson_pci_port80(void)
void hudson_lpc_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
/* Enable LPC controller */
outb(0xEC, 0xCD6);
@@ -123,7 +123,7 @@ void hudson_lpc_port80(void)
void hudson_lpc_decode(void)
{
- device_t dev;
+ pci_devfn_t dev;
u32 tmp = 0;
/* Enable I/O decode to LPC bus */
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index c5c1136..714796b 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -50,7 +50,7 @@ static inline void reset_system(void)
static void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c
index ee8c40c..f27fa87 100644
--- a/src/southbridge/intel/fsp_rangeley/early_smbus.c
+++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c
@@ -23,7 +23,7 @@
void enable_smbus(void)
{
- device_t dev;
+ pci_devfn_t dev;
/* Set the SMBus device statically. */
dev = PCI_DEV(0x0, 0x1f, 0x3);
diff --git a/src/southbridge/intel/fsp_rangeley/early_usb.c b/src/southbridge/intel/fsp_rangeley/early_usb.c
index edcd500..dfd8cc2 100644
--- a/src/southbridge/intel/fsp_rangeley/early_usb.c
+++ b/src/southbridge/intel/fsp_rangeley/early_usb.c
@@ -31,7 +31,7 @@
*/
void enable_usb_bar(void)
{
- device_t usb0 = SOC_EHCI1_DEV;
+ pci_devfn_t usb0 = SOC_EHCI1_DEV;
u32 cmd;
/* USB Controller 0 */
diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c
index 0605d10..1794393 100644
--- a/src/southbridge/intel/i82371eb/early_pm.c
+++ b/src/southbridge/intel/i82371eb/early_pm.c
@@ -23,7 +23,7 @@
void enable_pm(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 reg8;
u16 reg16;
diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c
index 69e967a..af6b14b 100644
--- a/src/southbridge/intel/i82371eb/early_smbus.c
+++ b/src/southbridge/intel/i82371eb/early_smbus.c
@@ -24,7 +24,7 @@
void enable_smbus(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 reg8;
u16 reg16;
diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
index 3a7d2b0..5bf87d8 100644
--- a/src/southbridge/intel/i82801dx/early_smbus.c
+++ b/src/southbridge/intel/i82801dx/early_smbus.c
@@ -22,7 +22,7 @@
void enable_smbus(void)
{
- device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
+ pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
printk(BIOS_DEBUG, "SMBus controller enabled\n");
/* set smbus iobase */
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index 821ed2c..bab59df 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -30,7 +30,7 @@
#include <arch/acpi.h>
#if !defined(__ASSEMBLER__)
-#if !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__) && !defined(__SIMPLE_DEVICE__)
#include "chip.h"
extern void i82801dx_enable(device_t dev);
#else
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 326a9e5..74d5a0c 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -240,7 +240,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c
index 2f9cdeb..47fe5f6 100644
--- a/src/southbridge/intel/i82801gx/early_smbus.c
+++ b/src/southbridge/intel/i82801gx/early_smbus.c
@@ -23,7 +23,7 @@
void enable_smbus(void)
{
- device_t dev;
+ pci_devfn_t dev;
/* Set the SMBus device statically. */
dev = PCI_DEV(0x0, 0x1f, 0x3);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index d4adc18..247ab92 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -16,7 +16,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
#define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
-#include <arch/acpi.h>
+#include <device/device.h>
/*
* It does not matter where we put the SMBus I/O base, as long as we
@@ -43,6 +43,9 @@
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
#include "chip.h"
+#if defined(__SIMPLE_DEVICE__)
+typedef uint32_t device_t;
+#endif
extern void i82801gx_enable(device_t dev);
void gpi_route_interrupt(u8 gpi, u8 mode);
#else
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