[coreboot-gerrit] Patch set updated for coreboot: src/arch: Capitalize CPU and ACPI
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Sun Aug 21 10:45:33 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16277
-gerrit
commit b0a8b0c9763c52e9a836519c7c33d01877da04e6
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Sun Aug 21 10:41:44 2016 +0200
src/arch: Capitalize CPU and ACPI
Change-Id: I37dfa853c3dbe93a52f6c37941b17717e22f6430
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/arch/arm64/stage_entry.S | 4 ++--
src/arch/x86/acpigen.c | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 7f113fb..7aeabe6 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -74,7 +74,7 @@ ENDPROC(cpu_get_exception_stack)
* any rmodules.
*/
ENTRY(arm64_c_environment)
- /* Set the exception stack for the cpu. */
+ /* Set the exception stack for the CPU. */
bl cpu_get_exception_stack
msr SPSel, #1
isb
@@ -84,7 +84,7 @@ ENTRY(arm64_c_environment)
msr SPSel, #0
isb
- /* Set the non-exception stack for the cpu. */
+ /* Set the non-exception stack for the CPU. */
bl cpu_get_stack
mov sp, x0
diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
index f35fe02..c978fe6 100644
--- a/src/arch/x86/acpigen.c
+++ b/src/arch/x86/acpigen.c
@@ -657,7 +657,7 @@ void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype)
void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size)
{
/*
- * acpi 4.0 section 6.4.3.4: 32-Bit Fixed Memory Range Descriptor
+ * ACPI 4.0 section 6.4.3.4: 32-Bit Fixed Memory Range Descriptor
* Byte 0:
* Bit7 : 1 => big item
* Bit6-0: 0000110 (0x6) => 32-bit fixed memory
@@ -688,7 +688,7 @@ void acpigen_write_register(acpi_addr_t *addr)
void acpigen_write_irq(u16 mask)
{
/*
- * acpi 3.0b section 6.4.2.1: IRQ Descriptor
+ * ACPI 3.0b section 6.4.2.1: IRQ Descriptor
* Byte 0:
* Bit7 : 0 => small item
* Bit6-3: 0100 (0x4) => IRQ port descriptor
@@ -702,7 +702,7 @@ void acpigen_write_irq(u16 mask)
void acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16)
{
/*
- * acpi 4.0 section 6.4.2.6: I/O Port Descriptor
+ * ACPI 4.0 section 6.4.2.6: I/O Port Descriptor
* Byte 0:
* Bit7 : 0 => small item
* Bit6-3: 1000 (0x8) => I/O port descriptor
More information about the coreboot-gerrit
mailing list