[coreboot-gerrit] New patch to review for coreboot: arch/riscv: Enable U-mode/S-mode counters (stime, etc.)

[Jonathan Neuschäfer (j.neuschaefer@gmx.net)]

Jonathan Neuschäfer (j.neuschaefer at gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16262

-gerrit

commit a7c298cff1d052f8c67e71856faacb756cac3667
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Fri Aug 19 12:10:20 2016 +0200

    arch/riscv: Enable U-mode/S-mode counters (stime, etc.)
    
    Change-Id: Ie62f60b2e237fa4921384e3894569ae29639f563
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
 src/arch/riscv/virtual_memory.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index fa30c54..c68ed4d 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -218,4 +218,8 @@ void mstatus_init(void)
 			| (1 << CAUSE_FAULT_STORE)
 			| (1 << CAUSE_USER_ECALL)
 	);
+
+	/* Enable all user/supervisor-mode counters */
+	write_csr(mscounteren, 0b111);
+	write_csr(mucounteren, 0b111);
 }