[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: make SPI support early stages
gerrit at coreboot.org
gerrit at coreboot.org
Fri Aug 19 03:09:53 CEST 2016
the following patch was just integrated into master:
commit 67d487e6874b854d5f265e7cc53504ce5319423b
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Aug 11 17:13:40 2016 -0500
soc/intel/skylake: make SPI support early stages
Using malloc() in SPI code is unnecessary as there's only
one SPI device that the SoC support code handles: boot
device. Therefore, use CAR to for the storage to work around
the current limiations of the SPI API which expects one to
return pointers to objects that are writable. Additionally,
include the SPI support code as well as its dependencies in
all the stages.
BUG=chrome-os-partner:56151
Change-Id: I0192ab59f3555deaf6a6878cc31c059c5c2b7d3f
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://review.coreboot.org/16196
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan at google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy at intel.com>
See https://review.coreboot.org/16196 for details.
-gerrit
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