[coreboot-gerrit] New patch to review for coreboot: google/reef: Save DIMM info from SMBIOS memory HOB

[Ravishankar Sarawadi (ravishankar.sarawadi@intel.com)]

Ravishankar Sarawadi (ravishankar.sarawadi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16249

-gerrit

commit 480b54529eec40a7bff6aa42ad73f6934fbf231e
Author: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
Date:   Thu Aug 18 13:34:18 2016 -0700

    google/reef: Save DIMM info from SMBIOS memory HOB
    
    Add support for SMBIOS memory HOB save.
    Add DIMM 'part_num' info to be saved as part of SMBIOS memory HOB.
    
    CQ-DEPEND=CL:16245,CL:16246
    BUG = chrome-os-partner:55505
    TEST = 'dmidecode -t 17' and 'mosys -k memory spd print all'
    Change-Id: I53b4a578f31c93b8921dea373842b8d998127508
    Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
---
 src/mainboard/google/reef/romstage.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c
index f9743b5..e8d8e16 100644
--- a/src/mainboard/google/reef/romstage.c
+++ b/src/mainboard/google/reef/romstage.c
@@ -82,12 +82,14 @@ static const struct lpddr4_sku skus[] = {
 		.ch1_rank_density = LP4_8Gb_DENSITY,
 		.ch0_dual_rank = 1,
 		.ch1_dual_rank = 1,
+		.part_num = "K4F6E304HB-MGCJ",
 	},
 	/* K4F8E304HB-MGCJ - both logical channels  */
 	[1] = {
 		.speed = LP4_SPEED_2400,
 		.ch0_rank_density = LP4_8Gb_DENSITY,
 		.ch1_rank_density = LP4_8Gb_DENSITY,
+		.part_num = "K4F8E304HB-MGCJ",
 	},
 	/*
 	 * MT53B512M32D2NP-062WT:C - both logical channels. While the parts
@@ -100,18 +102,21 @@ static const struct lpddr4_sku skus[] = {
 		.ch1_rank_density = LP4_8Gb_DENSITY,
 		.ch0_dual_rank = 1,
 		.ch1_dual_rank = 1,
+		.part_num = "MT53B512M32D2NP",
 	},
 	/* MT53B256M32D1NP-062 WT:C - both logical channels */
 	[3] = {
 		.speed = LP4_SPEED_2400,
 		.ch0_rank_density = LP4_8Gb_DENSITY,
 		.ch1_rank_density = LP4_8Gb_DENSITY,
+		.part_num = "MT53B256M32D1NP",
 	},
 	/* K4F8E304HB-MGCH - both logical channels */
 	[PROTO_SKU] = {
 		.speed = LP4_SPEED_2400,
 		.ch0_rank_density = LP4_8Gb_DENSITY,
 		.ch1_rank_density = LP4_8Gb_DENSITY,
+		.part_num = "K4F8E304HB-MGCH",
 	},
 };
 
@@ -121,9 +126,8 @@ static const struct lpddr4_cfg lp4cfg = {
 	.swizzle_config = &board_swizzle,
 };
 
-void mainboard_memory_init_params(struct FSPM_UPD *memupd)
+static int get_mem_sku(void)
 {
-	int mem_sku;
 	gpio_t pads[] = {
 		[3] = MEM_CONFIG3, [2] = MEM_CONFIG2,
 		[1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
@@ -133,7 +137,19 @@ void mainboard_memory_init_params(struct FSPM_UPD *memupd)
 	 * Read memory SKU id with internal pullups enabled to handle
 	 * proto boards with no SKU id pins.
 	 */
-	mem_sku = gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+	return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+}
+
+void mainboard_memory_init_params(struct FSPM_UPD *memupd)
+{
+	int mem_sku = get_mem_sku();
 
 	meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku);
 }
+
+void mainboard_save_dimm_info(void)
+{
+	int mem_sku = get_mem_sku();
+
+	save_lpddr4_dimm_info(&lp4cfg, mem_sku);
+}