[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Correct Cache as ram size

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 3ad63565a54f5ea3cdd866cbc6c70c67ad2757fe
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Sun Aug 14 15:48:33 2016 +0530

    soc/intel/skylake: Correct Cache as ram size
    
    DCACHE_RAM_SIZE_TOTAL is set to 0x40000 and is being used to
    set up CAR. Whereas DCACHE_RAM_SIZE which is set to 0x10000
    is used to calculate the _car_region_end in car.ld. If the FSP CAR
    requirement is greater than or even close to DCACHE_RAM_SIZE then,
    the CAR region for FSP will be determined to be below the overall
    CAR region boundary i.e, out of CAR memory range.
    
    This is working with FSP 1.1 because we provide the FspCarSize
    and FspCarBase explicitly in a UPD. Hence, FSP is still able to
    use the upper region of CAR memory for its purpose.
    However, it will be a problem in case of FSP2.0 where FSP usable CAR
    is calculated using _car_region_end.
    
    So, Remove the the use of DCACHE_RAM_SIZE_TOTAL and set
    DCACHE_RAM_SIZE to correct value i.e, 0x40000(256KB)
    
    Change-Id: Ie2cb8bb0705a37edb3414850d7659f8a3dd6958b
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Reviewed-on: https://review.coreboot.org/16236
    Reviewed-by: Martin Roth <martinroth at google.com>
    Tested-by: build bot (Jenkins)


See https://review.coreboot.org/16236 for details.

-gerrit