[coreboot-gerrit] New patch to review for coreboot: google/reef: Configure NFC gpios correctly before entering sleep

[Furquan Shaikh (furquan@google.com)]

Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16243

-gerrit

commit e318ceb27c669ed9dc3ba10a812b70bce5b12091
Author: Furquan Shaikh <furquan at google.com>
Date:   Wed Aug 17 16:18:05 2016 -0700

    google/reef: Configure NFC gpios correctly before entering sleep
    
    Before entering sleep, ensure that the NFC gpios are configured
    correctly to avoid leakage.
    
    BUG=chrome-os-partner:56281
    
    Change-Id: I2bb2e7ba468df445aa5f6c2b22ae0a74fcaa44f6
    Signed-off-by: Furquan Shaikh <furquan at google.com>
---
 src/mainboard/google/reef/gpio.h       | 6 ++++++
 src/mainboard/google/reef/smihandler.c | 4 ++++
 2 files changed, 10 insertions(+)

diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index be7f501..dbe7062 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -350,6 +350,12 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
 };
 
+/* GPIO settings before entering sleep. */
+static const struct pad_config sleep_gpio_table[] = {
+	PAD_CFG_GPO(GPIO_150, 0, DEEP),		/* NFC_RESET_ODL */
+	PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP),	/* NFC_INT_L */
+};
+
 /*
  * The proto boards didn't have memory SKU pins, but the same ones can be
  * utilized as post proto boards because the pins used were never connected
diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c
index e26c176..d33222b 100644
--- a/src/mainboard/google/reef/smihandler.c
+++ b/src/mainboard/google/reef/smihandler.c
@@ -19,7 +19,9 @@
 #include <ec/google/chromeec/smm.h>
 #include <soc/pm.h>
 #include <soc/smm.h>
+#include <soc/gpio.h>
 #include "ec.h"
+#include "gpio.h"
 
 void mainboard_smi_gpi_handler(const struct gpi_status *sts)
 {
@@ -29,6 +31,8 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts)
 
 void mainboard_smi_sleep(u8 slp_typ)
 {
+	gpio_configure_pads(sleep_gpio_table, ARRAY_SIZE(sleep_gpio_table));
+
 	if (slp_typ == ACPI_S3)
 		enable_gpe(GPIO_TIER_1_SCI);