[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add ASL methods for eMMC

[Vaibhav Shankar (vaibhav.shankar@intel.com)]

Vaibhav Shankar (vaibhav.shankar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16233

-gerrit

commit e2f37213cc08050b5657f1c5f351b8ab5ead505b
Author: Vaibhav Shankar <vaibhav.shankar at intel.com>
Date:   Mon Aug 15 11:32:26 2016 -0700

    soc/intel/apollolake: Add ASL methods for eMMC
    
    Implement PS0 and PS3 methods to support eMMC power gate
    in S0ix suspend and resume.
    
    BUG=chrome-os-partner:53876
    TEST=Suspend and Resume using 'echo freeze > /sys/power/state'.
    System should resume from S0ix.
    
    Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76
    Signed-off-by: Vaibhav Shankar <vaibhav.shankar at intel.com>
---
 src/soc/intel/apollolake/acpi/scs.asl         | 92 +++++++++++++++++++++++++++
 src/soc/intel/apollolake/acpi/southbridge.asl |  3 +
 2 files changed, 95 insertions(+)

diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl
new file mode 100644
index 0000000..7760c1a
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/scs.asl
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+scope (\_SB.PCI0) {
+  //0xD6 -  is the port address
+  //0x600 - is the dynamic clock gating control register offset (GENR)
+  OperationRegion (SBMM, SystemMemory, OR( OR (CONFIG_IOSF_BASE_ADDRESS,
+					ShiftLeft(0xD6, 16)), 0x0600), 0x18)
+    Field (SBMM, DWordAcc, NoLock, Preserve)
+    {
+      Offset (0x00),
+      GENR, 32,
+      Offset (0x08),
+          ,  5,
+      GRR3,  1,
+    }
+
+  //
+  // SCC power gate control method, this method must be serialized as multiple
+  // device will control
+  //the GENR register
+  //
+  // Arguments: (2)
+  //  Arg0: 0-AND  1-OR
+  //  Arg1: Value
+  Method (SCPG, 2, Serialized)
+  {
+    Name (TMP, 0x0)
+    if (LEqual(Arg0, 0x1)) {
+      Store (\_SB.PCI0.GENR, TMP)
+      Or    (TMP, Arg1, \_SB.PCI0.GENR)
+
+    } ElseIf(LEqual(Arg0, 0x0)) {
+      Store (\_SB.PCI0.GENR, TMP)
+      And   (TMP, Arg1, \_SB.PCI0.GENR)
+    }
+  }
+
+  //
+  // eMMC
+  //
+  Device(SDHA) {
+    Name (_ADR, 0x001C0000)
+    Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
+    Name (_UID, 1)
+    //Method for port80 debug
+    OperationRegion (POST, SystemIO, 0x80, 1)
+    Field (POST, ByteAcc, Lock, Preserve)
+    {
+      DBG0, 8
+    }
+
+    Method (_PS0, 0, NotSerialized)  // _PS0: Power State 0
+    {
+      // To enable port 80 debug
+      // Store(0xB1, DBG0)
+
+      // Clear clock gate
+      \_SB.PCI0.SCPG(0,0xFFFFFFBE) // Clear bit 6 and 0
+      Sleep (2)                    // Sleep 2 ms
+      // To enable port 80 debug
+      // Store(0xB2, DBG0)
+    }
+
+    Method (_PS3, 0, NotSerialized)          // _PS3: Power State 3
+    {
+      //
+      // Enable power gate
+      // To enable port 80 debug
+      // Store(0xB3, DBG0)
+
+      // Restore clock gate
+      \_SB.PCI0.SCPG(1,0x00000041) // restore bit 6 and 0
+
+      // To enable port 80 debug
+      //Store(0xB4, DBG0)
+    }
+
+  } // Device(SDHA)
+
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 5b29abb..391a531 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,5 +31,8 @@
 /* LPC */
 #include "lpc.asl"
 
+/* eMMC */
+#include "scs.asl"
+
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>