[coreboot-gerrit] Patch set updated for coreboot: WIP: soc/intel/apollolake: Cache cbmem region
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Mon Aug 15 09:03:18 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15456
-gerrit
commit 8bd6ed40f91f4b59d467d9d2efa57a66be3c3189
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Fri Jun 24 18:40:28 2016 -0700
WIP: soc/intel/apollolake: Cache cbmem region
Configure MTRRs to cache 8 MiB under cbmem_top. This allows caching
of FSP reserved memory and postcar stage. On CAR teardown flush and
write back caches to ensure coherency.
BUG=chrome-os-partner:51959
TEST=boot, notice cbmem showing MemoryInit getting ~30ms faster
Change-Id: I62aad238a3056f9bbe5327dfb33a2a1112d61194
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/exit_car.S | 14 ++++++++++++--
src/soc/intel/apollolake/include/soc/cpu.h | 4 ++++
src/soc/intel/apollolake/romstage.c | 8 ++++++++
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S
index c708244..8a6103e 100644
--- a/src/soc/intel/apollolake/exit_car.S
+++ b/src/soc/intel/apollolake/exit_car.S
@@ -33,6 +33,18 @@ chipset_teardown_car:
and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
wrmsr
+ /*
+ * Disable error signaling for certain type of CPU errors.
+ */
+ mov $MSR_MC5_CTL, %ecx
+ rdmsr
+ and $(~(PCU_HW_ERR_EN | PCU_UC_ERR_EN | PCU_FW_ERR_EN)), %eax
+ /* Flush all cache lines into the DRAM and invalidate caches */
+ wbinvd
+ /* Restore error signalling */
+ or $(PCU_HW_ERR_EN | PCU_UC_ERR_EN | PCU_FW_ERR_EN), %eax
+ wrmsr
+
#if IS_ENABLED(CONFIG_CAR_CQOS)
mov $MTRR_L2_QOS_MASK(0), %ecx
rdmsr
@@ -50,8 +62,6 @@ chipset_teardown_car:
and $~IA32_PQR_ASSOC_MASK, %edx
wrmsr
#endif
- /* invalidate cache contents. */
- invd
#if IS_ENABLED(CONFIG_CAR_NEM)
/* Knock down bit 1 then bit 0 of NEM control not combining steps. */
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 1efe6c4..c7511f1 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -38,6 +38,10 @@ void cache_qos_select_mask(uint8_t mask);
#define MSR_PREFETCH_CTL 0x1a4
#define PREFETCH_L1_DISABLE (1 << 0)
#define PREFETCH_L2_DISABLE (1 << 2)
+#define MSR_MC5_CTL 0x414
+#define PCU_HW_ERR_EN (1 << 0) /* signaling of PCU HW errors */
+#define PCU_UC_ERR_EN (1 << 1) /* signaling of PCU uC errors */
+#define PCU_FW_ERR_EN (1 << 2) /* signaling of PCU Pcode errors */
#define MTRR_L2_QOS_MASK(reg) (0xd10 + reg)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 8f17fdd..c18ce1b 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -104,6 +104,7 @@ asmlinkage void car_stage_entry(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
bool s3wake;
+ int mtrr;
struct chipset_power_state *ps = car_get_var_ptr(&power_state);
timestamp_add_now(TS_START_ROMSTAGE);
@@ -113,6 +114,13 @@ asmlinkage void car_stage_entry(void)
console_init();
+ mtrr = get_free_var_mtrr();
+ if (mtrr==-1)
+ printk(BIOS_CRIT, "no available MTRRs to cache cbmem!\n");
+ else
+ /* Make sure cbmem 8 MiB under CBMEM is cachable */
+ set_var_mtrr(mtrr, 0x7a800000, 8*MiB, MTRR_TYPE_WRBACK);
+
s3wake = fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);
if (postcar_frame_init(&pcf, 1*KiB))
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