[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: make SPI support early stages
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Fri Aug 12 23:28:36 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16196
-gerrit
commit 589efdd9f22f0ec89d617efffba1ae846b240c66
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Aug 11 17:13:40 2016 -0500
soc/intel/skylake: make SPI support early stages
Using malloc() in SPI code is unnecessary as there's only
one SPI device that the SoC support code handles: boot
device. Therefore, use CAR to for the storage to work around
the current limiations of the SPI API which expects one to
return pointers to objects that are writable. Additionally,
include the SPI support code as well as its dependencies in
all the stages.
BUG=chrome-os-partner:56151
Change-Id: I0192ab59f3555deaf6a6878cc31c059c5c2b7d3f
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/skylake/Makefile.inc | 3 +++
src/soc/intel/skylake/flash_controller.c | 22 +++++++++++-----------
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 7b27c57..fa7a693 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -14,6 +14,7 @@ bootblock-y += bootblock/cache_as_ram.S
bootblock-y += bootblock/cpu.c
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/systemagent.c
+bootblock-y += flash_controller.c
bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
bootblock-y += gpio.c
bootblock-y += monotonic_timer.c
@@ -23,6 +24,8 @@ bootblock-y += pmutil.c
bootblock-y += tsc_freq.c
bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
+verstage-y += flash_controller.c
+verstage-y += pch.c
verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
romstage-y += flash_controller.c
diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index 9c2378b..6601e6c 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -13,6 +13,7 @@
*/
/* This file is derived from the flashrom project. */
+#include <arch/early_variables.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
@@ -341,15 +342,17 @@ int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg)
return 0;
}
+static struct spi_slave boot_spi CAR_GLOBAL;
+static struct spi_flash boot_flash CAR_GLOBAL;
+
static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi)
{
struct spi_flash *flash;
- flash = malloc(sizeof(*flash));
- if (!flash) {
- printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
- return NULL;
- }
+ flash = car_get_var_ptr(&boot_flash);
+
+ /* Ensure writes can take place to the flash. */
+ spi_init();
flash->spi = spi;
flash->name = "Opaque HW-sequencing";
@@ -369,14 +372,11 @@ static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi)
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
{
- struct spi_slave *slave = malloc(sizeof(*slave));
-
- if (!slave) {
- printk(BIOS_DEBUG, "PCH SPI: Bad allocation\n");
+ /* This is special hardware. We expect bus 0 and CS line 0 here. */
+ if ((bus != 0) || (cs != 0))
return NULL;
- }
- memset(slave, 0, sizeof(*slave));
+ struct spi_slave *slave = car_get_var_ptr(&boot_spi);
slave->bus = bus;
slave->cs = cs;
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