[coreboot-gerrit] Patch set updated for coreboot: intel/amenia: Update flash size to 16MB
Bora Guvendik (bora.guvendik@intel.com)
gerrit at coreboot.org
Mon Aug 8 20:57:25 CEST 2016
Bora Guvendik (bora.guvendik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16083
-gerrit
commit 8776a4369b52cdbd7600094a6592e9fdd7fbda0b
Author: Bora Guvendik <bora.guvendik at intel.com>
Date: Fri Aug 5 14:18:20 2016 -0700
intel/amenia: Update flash size to 16MB
Update image flash size to 16MB and update image layout
in flashmap descriptor file.
BUG=chrome-os-partner:51844
TEST=Boot to chrome
Change-Id: Ibdfb2949d06aedc38ddcef1078c2d14abcfa2dac
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
src/mainboard/intel/amenia/Kconfig | 22 ++++++---
src/mainboard/intel/amenia/chromeos.fmd | 86 +++++++++++++++++++--------------
2 files changed, 67 insertions(+), 41 deletions(-)
diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig
index 2a4189e..502465b 100644
--- a/src/mainboard/intel/amenia/Kconfig
+++ b/src/mainboard/intel/amenia/Kconfig
@@ -3,18 +3,20 @@ if BOARD_INTEL_AMENIA
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_INTEL_APOLLOLAKE
- select BOARD_ROMSIZE_KB_8192
- select MAINBOARD_HAS_CHROMEOS
+ select BOARD_ROMSIZE_KB_16384
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
- select EC_GOOGLE_CHROMEEC_PD
select HAVE_ACPI_TABLES
+ select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LPC_TPM
select HAVE_ACPI_RESUME
- select MAINBOARD_HAS_CHROMEOS
select SYSTEM_TYPE_LAPTOP
select TPM_ON_FAST_SPI
+config BOOT_MEDIA_SPI_BUS
+ int
+ default 0
+
config CHROMEOS
select LID_SWITCH
@@ -22,6 +24,10 @@ config MAINBOARD_DIR
string
default intel/amenia
+config MAINBOARD_FAMILY
+ string
+ default "Intel_Amenia"
+
config MAINBOARD_PART_NUMBER
string
default "Amenia"
@@ -34,9 +40,9 @@ config FMAP_FILE
string
default "amenia"
-config PREBUILT_SPI_IMAGE
+config FMDFILE
string
- default "amenia.bin.orig.a0"
+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
config MAX_CPUS
int
@@ -54,4 +60,8 @@ config DRIVERS_GENERIC_MAX98357A
config DRIVERS_I2C_DA7219
default y
+config UART_FOR_CONSOLE
+ int
+ default 2
+
endif # BOARD_INTEL_AMENIA
diff --git a/src/mainboard/intel/amenia/chromeos.fmd b/src/mainboard/intel/amenia/chromeos.fmd
index a620aa4..bebee33 100644
--- a/src/mainboard/intel/amenia/chromeos.fmd
+++ b/src/mainboard/intel/amenia/chromeos.fmd
@@ -1,36 +1,52 @@
-FLASH 8M {
- WP_RO 4M {
- SI_ALL 2M {
- SI_DESC 4K
- bootblock at 509056 32K
- }
- RO_SECTION at 2M 2M {
- FMAP 2K
- RO_FRID 0x40
- RO_VPD @4K 16K
- COREBOOT(CBFS)
- SIGN_CSE at 0x180000 64K
- GBB
- }
- }
- MISC_RW {
- RW_MRC_CACHE 64K
- RW_ELOG 16K
- RW_SHARED 16K {
- SHARED_DATA 8K
- VBLOCK_DEV 8K
- }
- RW_VPD 8K
- }
- RW_SECTION_A 0xf0000 {
- VBLOCK_A 64K
- FW_MAIN_A(CBFS) 768K
- RW_FWID_A 64
- }
- RW_SECTION_B 0xf0000 {
- VBLOCK_B 64K
- FW_MAIN_B(CBFS) 768K
- RW_FWID_B 64
- }
- DEVICE_EXTENSION at 7M 1M
+FLASH 16M {
+ WP_RO at 0x0 0x800000 {
+ SI_DESC at 0x0 0x1000
+ IFWI at 0x1000 0x1ff000
+ RO_SECTION at 0x200000 0x600000 {
+ RO_VPD at 0x0 0x4000
+ FMAP at 0x4000 0x800
+ RO_FRID at 0x4800 0x40
+ RO_FRID_PAD at 0x4840 0x7c0
+ COREBOOT(CBFS)@0x5000 0x17b000
+ GBB at 0x180000 0x40000
+ RO_UNUSED_1 at 0x1c0000 0x400000
+ # logical boot partition 2. Remove with updated CSE
+ SIGN_CSE at 0x5c0000 0x10000
+ RO_UNUSED_2 at 0x5d0000 0x30000
+ }
+ }
+ MISC_RW at 0x800000 0x1a000 {
+ RW_MRC_CACHE at 0x0 0x10000
+ RW_ELOG at 0x10000 0x4000
+ RW_SHARED at 0x14000 0x4000 {
+ SHARED_DATA at 0x0 0x2000
+ VBLOCK_DEV at 0x2000 0x2000
+ }
+ RW_VPD at 0x18000 0x2000
+ }
+ RW_SECTION_A at 0x81a000 0x28f800 {
+ VBLOCK_A at 0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x27f7c0
+ RW_FWID_A at 0x28f7c0 0x40
+ }
+ RW_SECTION_B at 0xaa9800 0x28f800 {
+ VBLOCK_B at 0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x27f7c0
+ RW_FWID_B at 0x28f7c0 0x40
+ }
+ RW_NVRAM at 0xd39000 0x6000
+ RW_LEGACY(CBFS)@0xd3f000 0x200000
+ BIOS_UNUSABLE at 0xf3f000 0x40000
+ DEVICE_EXTENSION at 0xf7f000 0x80000
+ # Currently, it is required that the BIOS region be a multiple of 8KiB.
+ # This is required so that the recovery mechanism can find SIGN_CSE
+ # region aligned to 4K at the center of BIOS region. Since the
+ # descriptor at the beginning uses 4K and BIOS starts at an offset of
+ # 4K, a hole of 4K is created towards the end of the flash to compensate
+ # for the size requirement of BIOS region.
+ # FIT tool thus creates descriptor with following regions:
+ # Descriptor --> 0 to 4K
+ # BIOS --> 4K to 0xf7f000
+ # Device ext --> 0xf7f000 to 0xfff000
+ UNUSED_HOLE at 0xfff000 0x1000
}
More information about the coreboot-gerrit
mailing list