[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Add support for serial console based ACPI debug

Fri Aug 5 18:48:23 CEST 2016

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16070

-gerrit

commit 41cbffa85b3e4efa57606ecf9bd97b9fc8d472c7
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Fri Aug 5 18:25:55 2016 +0530

    soc/intel/skylake: Add support for serial console based ACPI debug
    
    This patch enables serial debug functionality for ASL code based on
    UART type(legacy/LPSS).
    
    From Skylake onwards all Intel platform uses LPSS based UART for serial
    console hence provide option to redirect ASL log over LPSS UART.
    
    Example:
    Name (OBJ, 0x12)
    APRT (OBJ)
    APRT ("CORE BOOT")
    
    Output:
    0x12
    CORE BOOT
    
    BUG=none
    BRANCH=none
    TEST=Built and boot kunimitsu to ensure to be able to get ASL console log.
    
    Change-Id: I18c65654b8eb1ac27af1f283d413376fd79d47db
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 src/soc/intel/skylake/Kconfig             |   6 ++
 src/soc/intel/skylake/acpi/acpi_debug.asl | 104 ++++++++++++++++++++++++++++++
 src/soc/intel/skylake/acpi/platform.asl   |   5 ++
 3 files changed, 115 insertions(+)

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 0ecc80d..9723b4f 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -61,6 +61,12 @@ config CHROMEOS
 	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 	select VIRTUAL_DEV_SWITCH
 
+config ACPI_CONSOLE
+	bool
+	default n
+	help
+	  Provide a mechanism for serial console based ACPI debug.
+
 config BOOTBLOCK_RESETS
 	string
 	default "soc/intel/common/reset.c"
diff --git a/src/soc/intel/skylake/acpi/acpi_debug.asl b/src/soc/intel/skylake/acpi/acpi_debug.asl
new file mode 100644
index 0000000..d966117
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/acpi_debug.asl
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+	Mutex(MMUX, 0)
+
+	Method (APRT, 1, Serialized)
+	{
+		Name(OPDT, 0)
+		Name(INDX, 0)
+		Name(LENG, 0)
+		Name(ADBG, Buffer(256) {0})
+		Name(CRLF, Buffer() {0x0D, 0x0A})
+
+		If (LEqual(ObjectType(Arg0), 1)) { /* Integer */
+			ToHexString(Arg0, ADBG)
+		} ElseIf (LEqual(ObjectType(Arg0), 2)) { /* String */
+			Store(Arg0, ADBG)
+		} ElseIf (LEqual(ObjectType(Arg0), 3)) { /* Buffer */
+			ToHexString(Arg0, ADBG)
+		} Else {
+			Store("This type of object is not supported", ADBG)
+		}
+
+		/* Append CRLF at the end of string */
+		While (LNotEqual(DeRefOf(Index(ADBG, INDX)), 0))
+		{
+			Increment (INDX)
+		}
+		Store (0x0D, Index(ADBG, INDX)) /* Insert CR */
+		Increment (INDX)
+		Store (0x0A, Index(ADBG, INDX)) /* Insert LF */
+		Increment (INDX)
+		Store (INDX, LENG) /* Length of the String */
+
+#if CONFIG_DRIVERS_UART_8250MEM_32
+		OperationRegion (UBAR, SystemMemory, UART_DEBUG_BASE_ADDRESS, 24)
+		Field (UBAR, AnyAcc, NoLock, Preserve)
+		{
+			TDR, 32,	/* Transmit Data Register BAR + 0x000 */
+			IER, 32,	/* Interrupt Enable Register BAR + 0x004 */
+			IIR, 32,	/* Interrupt Identification Register BAR + 0x008 */
+			LCR, 32,	/* Line Control Register BAR + 0x00C */
+			MCR, 32,	/* Modem Control Register BAR + 0x010 */
+			LSR, 32		/* Line Status Register BAR + 0x014 */
+		}
+#else
+		OperationRegion (UBAR, SystemIO, 0x3F8, 6)
+		Field (UBAR, ByteAcc, NoLock, Preserve)
+		{
+			TDR, 8,	/* Transmit Data Register (3F8) */
+			IER, 8,	/* Interrupt Enable Register (3F9) */
+			IIR, 8,	/* Interrupt Identification Register (3FA) */
+			LCR, 8,	/* Line Control Register (3FB) */
+			MCR, 8,	/* Modem Control Register (3FC) */
+			LSR, 8	/* Line Status Register (3FD) */
+		}
+#endif
+
+		Store (Acquire(MMUX, 1000), Local0)	/*Save Acquire result so we can check for Mutex acquired */
+		If (LEqual (Local0, Zero))	/* Check for Mutex acquired */
+		{
+			/* Enable Baud Rate Divisor Latch and Set Word length to 8 bit*/
+			Store (0x83, LCR)
+			Store (0x01, IIR)
+			Store (0x03, MCR)
+
+			/* Configure baud rate to 115200 */
+			Store (0x01, TDR)
+			Store (0x00, IER)
+			Store (0x03, LCR) /* Disable Baud Rate Divisor Latch */
+
+			Store (0x00, INDX)
+			While (LLess (INDX, LENG))
+			{
+				/* Wait for the transmitter t to be ready */
+				While (1)
+				{
+					And (LSR, 0x20, OPDT)
+					If (LNotEqual(OPDT, 0))
+					{
+						Break
+					}
+				}
+				Store (DeRefOf (Index (ADBG, INDX)), TDR)
+				Increment(INDX)
+			}
+			Release(MMUX)
+		}
+} /* End of APRT */
+
diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl
index 39debe1..553cc1a 100644
--- a/src/soc/intel/skylake/acpi/platform.asl
+++ b/src/soc/intel/skylake/acpi/platform.asl
@@ -18,6 +18,11 @@
 /* Enable ACPI _SWS methods */
 #include <soc/intel/common/acpi/acpi_wake_source.asl>
 
+#if CONFIG_ACPI_CONSOLE
+/* Enable ACPI Debug methods */
+#include "acpi_debug.asl"
+#endif
+
 /* The APM port can be used for generating software SMIs */
 
 OperationRegion (APMP, SystemIO, 0xb2, 2)

