[coreboot-gerrit] Patch merged into coreboot/master: arch/riscv: Add include/arch/barrier.h

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit cc5be8b72ba5b072030fdd1d382d7156da43114f
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Tue Jul 26 01:54:34 2016 +0200

    arch/riscv: Add include/arch/barrier.h
    
    mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/.
    It is currently provided by atomic.h, but I think it fits better into
    barrier.h.
    
    The "fence" instruction represents a full memory fence, as opposed to
    variants such as "fence r, rw" which represent a partial fence. An
    operating system might want to use precisely the right fence, but
    coreboot doesn't need this level of performance at the cost of
    simplicity.
    
    Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
    Reviewed-on: https://review.coreboot.org/15830
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>


See https://review.coreboot.org/15830 for details.

-gerrit