[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: clarify Fast SPI CS2 pad configuration

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14531

-gerrit

commit 3f7d6653ab9918579b631f32519608cc804efdf6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Apr 27 23:05:52 2016 -0500

    soc/intel/apollolake: clarify Fast SPI CS2 pad configuration
    
    The pad for CS2 of the Fast SPI interface needs to be configured for
    automatic MMIO translation when a SPI TPM is utilized. Instead of
    unconditionally configuring that pad under LPC_TPM provide a explicit
    Kconfig for a mainboard to select.
    
    Change-Id: Ia94b90e12d71a4b849359188a853f7e036cc583b
    Signed-off-by: Aaron Durbin <adurbin at chormium.org>
---
 src/mainboard/intel/amenia/Kconfig             | 1 +
 src/soc/intel/apollolake/Kconfig               | 8 ++++++++
 src/soc/intel/apollolake/bootblock/bootblock.c | 2 +-
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig
index be98b86..b2c1a8c 100644
--- a/src/mainboard/intel/amenia/Kconfig
+++ b/src/mainboard/intel/amenia/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_LPC_TPM
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select TPM_ON_FAST_SPI
 
 config CHROMEOS
 	bool
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 7cd548b..bdb8eeb 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -41,6 +41,14 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_HARD_RESET
 	select SOC_INTEL_COMMON
 
+config TPM_ON_FAST_SPI
+	bool
+	default n
+	select LPC_TPM
+	help
+	 TPM part is conntected on Fast SPI interface, but the LPC MMIO
+	 TPM transactions are decoded and serialized over the SPI interface.
+
 config SOC_INTEL_COMMON_RESET
 	bool
 	default y
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 2456455..abb713e 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -102,7 +102,7 @@ void bootblock_soc_early_init(void)
 	if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
 		soc_console_uart_init();
 
-	if (IS_ENABLED(CONFIG_LPC_TPM))
+	if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))
 		tpm_enable();
 
 	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC))