[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMES builds
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Wed Apr 27 23:10:38 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14471
-gerrit
commit 17ecc076bfddde0712099cb9bab5c91b5f8d7bfe
Author: Lance Zhao <lijian.zhao at intel.com>
Date: Tue Apr 19 18:04:21 2016 -0700
soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMES builds
Add chromeos required GNVS feature. The GNVS table stays in both CBMEM
and ACPI DSDT tables.
Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/acpi.c | 29 ++++++++++++++++++++++
src/soc/intel/apollolake/acpi/globalnvs.asl | 35 +++++++++++++++++++++++++++
src/soc/intel/apollolake/chip.c | 6 +++++
src/soc/intel/apollolake/include/soc/acpi.h | 2 ++
src/soc/intel/apollolake/include/soc/nvs.h | 37 +++++++++++++++++++++++++++++
src/soc/intel/apollolake/lpc.c | 1 +
6 files changed, 110 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 7d28313..a5d1dfa 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -16,12 +16,15 @@
*/
#include <arch/acpi.h>
+#include <arch/acpigen.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
+#include <cbmem.h>
#include <cpu/x86/smm.h>
#include <soc/acpi.h>
#include <soc/iomap.h>
#include <soc/pm.h>
+#include <soc/nvs.h>
unsigned long acpi_fill_mcfg(unsigned long current)
{
@@ -125,3 +128,29 @@ unsigned long southbridge_write_acpi_tables(device_t device,
{
return acpi_write_hpet(device, current, rsdp);
}
+
+static void acpi_create_gnvs(struct global_nvs_t *gnvs)
+{
+ if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ /* Initialize Verified Boot data */
+ chromeos_init_vboot(&gnvs->chromeos);
+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+ }
+}
+
+void southbridge_inject_dsdt(device_t device)
+{
+ struct global_nvs_t *gnvs;
+
+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+
+ if (gnvs) {
+ acpi_create_gnvs(gnvs);
+ acpi_save_gnvs((uintptr_t)gnvs);
+
+ /* Add it to DSDT. */
+ acpigen_write_scope("\\");
+ acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
+ acpigen_pop_len();
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
new file mode 100644
index 0000000..2ef5031
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * NOTE: The layout of the GNVS structure below must match the layout in
+ * soc/intel/apollolake/include/soc/nvs.h !!!
+ *
+ */
+
+External (NVSA)
+
+OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Nothing here yet, folks */
+ Offset (0x00),
+
+ /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
+ Offset (0x100),
+ #include <vendorcode/google/chromeos/acpi/gnvs.asl>
+}
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index d2a1e0d..6e0a90f 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -17,6 +17,7 @@
*/
#include <bootstate.h>
+#include <cbmem.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <device/device.h>
@@ -26,6 +27,7 @@
#include <memrange.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
+#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include "chip.h"
@@ -65,11 +67,15 @@ static void enable_dev(device_t dev)
static void soc_init(void *data)
{
struct range_entry range;
+ struct global_nvs_t *gnvs;
/* TODO: tigten this resource range */
/* TODO: fix for S3 resume, as this would corrupt OS memory */
range_entry_init(&range, 0x200000, 4ULL*GiB, 0);
fsp_silicon_init(&range);
+
+ /* Allocate ACPI NVS in CBMEM */
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
}
void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h
index 2d20805..3605cc3 100644
--- a/src/soc/intel/apollolake/include/soc/acpi.h
+++ b/src/soc/intel/apollolake/include/soc/acpi.h
@@ -25,4 +25,6 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt);
unsigned long southbridge_write_acpi_tables(device_t device,
unsigned long current, struct acpi_rsdp *rsdp);
+void southbridge_inject_dsdt(device_t device);
+
#endif /* _SOC_APOLLOLAKE_ACPI_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
new file mode 100644
index 0000000..8b3a3af
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * NOTE: The layout of the global_nvs_t structure below must match the layout
+ * in soc/intel/apollolake/acpi/globalnvs.asl !!!
+ *
+ */
+
+#ifndef _SOC_APOLLOLAKE_NVS_H_
+#define _SOC_APOLLOLAKE_NVS_H_
+
+#include <vendorcode/google/chromeos/gnvs.h>
+
+struct global_nvs_t {
+ /* Miscellaneous */
+ uint8_t unused[256];
+
+ /* ChromeOS specific (0x100 - 0xfff) */
+ chromeos_acpi_t chromeos;
+} __attribute__((packed));
+
+#endif /* _SOC_APOLLOLAKE_NVS_H_ */
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 6e366e0..06ca0db 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -86,6 +86,7 @@ static struct device_operations device_ops = {
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.write_acpi_tables = southbridge_write_acpi_tables,
+ .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.init = &lpc_init
};
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