[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add cache for BIOS ROM
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Tue Apr 26 19:14:25 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14480
-gerrit
commit 1aee866b279ddaca3335a781cd27b9085b62f945
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Sat Apr 23 12:31:01 2016 -0700
soc/intel/apollolake: Add cache for BIOS ROM
Enable caching of BIOS region with variable MTRR. This is most
useful if enabled early such as in bootblock.
Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/cpu/x86/mtrr/Makefile.inc | 1 +
src/soc/intel/apollolake/bootblock/bootblock.c | 21 +++++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc
index 9b7207b..e6e9c50 100644
--- a/src/cpu/x86/mtrr/Makefile.inc
+++ b/src/cpu/x86/mtrr/Makefile.inc
@@ -1,2 +1,3 @@
ramstage-y += mtrr.c
romstage-y += earlymtrr.c
+bootblock-y += earlymtrr.c
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 78ce65f..ff84ae2 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -16,7 +16,9 @@
*/
#include <arch/cpu.h>
#include <bootblock_common.h>
+#include <cpu/x86/mtrr.h>
#include <device/pci.h>
+#include <lib.h>
#include <soc/bootblock.h>
#include <soc/cpu.h>
#include <soc/gpio.h>
@@ -75,6 +77,24 @@ void asmlinkage bootblock_c_entry(void)
main();
}
+static void cache_bios_region(void)
+{
+ int mtrr;
+ uint32_t rom_size, alignment;
+
+ mtrr = get_free_var_mtrr();
+
+ if (mtrr==-1)
+ return;
+
+ /* Only the IFD BIOS region is memory mapped (at top of 4G) */
+ rom_size = CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START;
+ /* Round to power of two */
+ alignment = 1 << (log2_ceil(rom_size));
+ rom_size = ALIGN_UP(rom_size, alignment);
+ set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT);
+}
+
void bootblock_soc_early_init(void)
{
/* Prepare UART for serial console. */
@@ -87,4 +107,5 @@ void bootblock_soc_early_init(void)
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC))
early_lpc_enable();
+ cache_bios_region();
}
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