[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Enable RAM cache for cbmem region in ramstage
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Tue Apr 26 19:01:27 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14095
-gerrit
commit 0c09663ebf7ab12aa713d3b65c5d36d847acfc6c
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Sat Apr 23 13:15:51 2016 -0700
soc/intel/apollolake: Enable RAM cache for cbmem region in ramstage
Use postcar infrastructure to enable caching of area where ramstage
runs.
Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/romstage.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 640026a..9dcb26a 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -16,12 +16,14 @@
* GNU General Public License for more details.
*/
+#include <assert.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/symbols.h>
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
+#include <cpu/x86/mtrr.h>
#include <device/pci_def.h>
#include <fsp/api.h>
#include <fsp/util.h>
@@ -81,6 +83,7 @@ asmlinkage void car_stage_entry(void)
struct range_entry fsp_mem, reg_car;
struct postcar_frame pcf;
size_t mrc_data_size;
+ uintptr_t top_of_ram;
printk(BIOS_DEBUG, "Starting romstage...\n");
@@ -122,6 +125,16 @@ asmlinkage void car_stage_entry(void)
if (postcar_frame_init(&pcf, 1*KiB))
die("Unable to initialize postcar frame.\n");
+ /*
+ * We need to make sure ramstage will be run cached. At this point exact
+ * location of ramstage in cbmem is not known. Instruct postcar to cache
+ * 16 megs under cbmem top which is a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t) cbmem_top();
+ /* cbmem_top() needs to be at least 16 MiB aligned */
+ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
+
run_postcar_phase(&pcf);
}
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