[coreboot-gerrit] Patch set updated for coreboot: nb/amd/mct_ddr3: Report correct DIMM in MRS setup routines

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14501

-gerrit

commit 0dae23f6b19b1ce668ec36b9988fc8f9b4b23940
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Sun Apr 24 20:27:28 2016 -0500

    nb/amd/mct_ddr3: Report correct DIMM in MRS setup routines
    
    The wrong DIMM number was used in the initial non-target MRS
    setup routines.  This had no functional impact other than to
    print the wrong DIMM number in the DDR3 verbose debug output.
    
    Change-Id: I480118ed00e1786a06e641a56f0fb19cd87f92eb
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index 6e1c850..c6ec905 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 - 2016 Raptor Engineering, LLC
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -779,7 +779,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
 
 					/* Retrieve normal settings of the MRS control word and clear Rtt_Nom */
 					if (is_fam15h()) {
-						tempW = mct_MR1(pMCTstat, pDCTstat, dct, dimm*2+rank) & 0xffff;
+						tempW = mct_MR1(pMCTstat, pDCTstat, dct, currDimm*2+rank) & 0xffff;
 						tempW &= ~(0x0244);
 					} else {
 						/* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */
@@ -862,7 +862,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
 
 					/* Retrieve normal settings of the MRS control word and clear Rtt_WR */
 					if (is_fam15h()) {
-						tempW = mct_MR2(pMCTstat, pDCTstat, dct, dimm*2+rank) & 0xffff;
+						tempW = mct_MR2(pMCTstat, pDCTstat, dct, currDimm*2+rank) & 0xffff;
 						tempW &= ~(0x0600);
 					} else {
 						/* program MrsAddress[7,6,5:3]=SRT,ASR,CWL,