[coreboot-gerrit] New patch to review for coreboot: vendorcode/intel: Move FSP code out of drivers and into vendorcode
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Sun Apr 24 20:30:43 CEST 2016
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14499
-gerrit
commit 6faa9c8bcfa70d308fd1462c87fe73b6093a7657
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date: Sun Apr 24 11:26:37 2016 -0700
vendorcode/intel: Move FSP code out of drivers and into vendorcode
Intel's vendorcode, despite not being a driver, was originally committed into
drivers. In order to keep FSP code from being spread all across the code base,
move the common FSP code from src/drivers/fsp<version>/ over into the vendor
code at src/vendorcode/intel/fsp/fsp<version>/common.
This also fixes an outstanding issue where Intel's FSP Kconfig options started
showing up twice, once in the SOC sub menu (where they belong), and once under
the drivers sub menu.
Change-Id: Ia70ee8d6afb7990aaf92b1b6ed9547ced65d53cd
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
src/Kconfig | 6 +-
src/drivers/intel/fsp1_0/Kconfig | 127 -------
src/drivers/intel/fsp1_0/Makefile.inc | 49 ---
src/drivers/intel/fsp1_0/cache_as_ram.inc | 124 ------
src/drivers/intel/fsp1_0/fastboot_cache.c | 257 -------------
src/drivers/intel/fsp1_0/fsp_util.c | 348 -----------------
src/drivers/intel/fsp1_0/fsp_util.h | 131 -------
src/drivers/intel/fsp1_0/fsp_values.h | 37 --
src/drivers/intel/fsp1_0/hob.c | 265 -------------
src/drivers/intel/fsp1_1/Kconfig | 118 ------
src/drivers/intel/fsp1_1/Makefile.inc | 59 ---
src/drivers/intel/fsp1_1/after_raminit.S | 171 ---------
src/drivers/intel/fsp1_1/cache_as_ram.inc | 225 -----------
src/drivers/intel/fsp1_1/car.c | 123 ------
src/drivers/intel/fsp1_1/fsp_gop.c | 96 -----
src/drivers/intel/fsp1_1/fsp_relocate.c | 53 ---
src/drivers/intel/fsp1_1/fsp_util.c | 299 ---------------
src/drivers/intel/fsp1_1/hob.c | 325 ----------------
src/drivers/intel/fsp1_1/include/fsp/api.h | 35 --
src/drivers/intel/fsp1_1/include/fsp/car.h | 49 ---
src/drivers/intel/fsp1_1/include/fsp/gma.h | 178 ---------
src/drivers/intel/fsp1_1/include/fsp/gop.h | 23 --
src/drivers/intel/fsp1_1/include/fsp/memmap.h | 47 ---
src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 36 --
src/drivers/intel/fsp1_1/include/fsp/romstage.h | 98 -----
src/drivers/intel/fsp1_1/include/fsp/soc_binding.h | 39 --
src/drivers/intel/fsp1_1/include/fsp/stack.h | 31 --
.../intel/fsp1_1/include/fsp/uefi_binding.h | 35 --
src/drivers/intel/fsp1_1/include/fsp/util.h | 102 -----
src/drivers/intel/fsp1_1/raminit.c | 320 ----------------
src/drivers/intel/fsp1_1/ramstage.c | 223 -----------
src/drivers/intel/fsp1_1/romstage.c | 420 ---------------------
src/drivers/intel/fsp1_1/romstage_after_verstage.S | 48 ---
src/drivers/intel/fsp1_1/stack.c | 178 ---------
src/drivers/intel/fsp1_1/stage_cache.c | 28 --
src/drivers/intel/fsp1_1/vbt.c | 42 ---
src/drivers/intel/fsp1_1/verstage.c | 24 --
src/drivers/intel/fsp2_0/Kconfig | 6 -
src/drivers/intel/fsp2_0/Makefile.inc | 28 --
src/drivers/intel/fsp2_0/graphics.c | 105 ------
src/drivers/intel/fsp2_0/hand_off_block.c | 305 ---------------
src/drivers/intel/fsp2_0/include/fsp/api.h | 110 ------
src/drivers/intel/fsp2_0/include/fsp/info_header.h | 56 ---
src/drivers/intel/fsp2_0/include/fsp/util.h | 42 ---
src/drivers/intel/fsp2_0/memory_init.c | 73 ----
src/drivers/intel/fsp2_0/notify.c | 40 --
src/drivers/intel/fsp2_0/silicon_init.c | 59 ---
src/drivers/intel/fsp2_0/util.c | 138 -------
src/vendorcode/intel/Kconfig | 4 +
src/vendorcode/intel/Makefile.inc | 4 +
src/vendorcode/intel/fsp/fsp1_0/common/Kconfig | 127 +++++++
.../intel/fsp/fsp1_0/common/Makefile.inc | 49 +++
.../intel/fsp/fsp1_0/common/cache_as_ram.inc | 124 ++++++
.../intel/fsp/fsp1_0/common/fastboot_cache.c | 257 +++++++++++++
src/vendorcode/intel/fsp/fsp1_0/common/fsp_util.c | 348 +++++++++++++++++
src/vendorcode/intel/fsp/fsp1_0/common/fsp_util.h | 131 +++++++
.../intel/fsp/fsp1_0/common/fsp_values.h | 37 ++
src/vendorcode/intel/fsp/fsp1_0/common/hob.c | 265 +++++++++++++
src/vendorcode/intel/fsp/fsp1_1/common/Kconfig | 118 ++++++
.../intel/fsp/fsp1_1/common/Makefile.inc | 59 +++
.../intel/fsp/fsp1_1/common/after_raminit.S | 171 +++++++++
.../intel/fsp/fsp1_1/common/cache_as_ram.inc | 225 +++++++++++
src/vendorcode/intel/fsp/fsp1_1/common/car.c | 123 ++++++
src/vendorcode/intel/fsp/fsp1_1/common/fsp_gop.c | 96 +++++
.../intel/fsp/fsp1_1/common/fsp_relocate.c | 53 +++
src/vendorcode/intel/fsp/fsp1_1/common/fsp_util.c | 299 +++++++++++++++
src/vendorcode/intel/fsp/fsp1_1/common/hob.c | 325 ++++++++++++++++
.../intel/fsp/fsp1_1/common/include/fsp/api.h | 35 ++
.../intel/fsp/fsp1_1/common/include/fsp/car.h | 49 +++
.../intel/fsp/fsp1_1/common/include/fsp/gma.h | 178 +++++++++
.../intel/fsp/fsp1_1/common/include/fsp/gop.h | 23 ++
.../intel/fsp/fsp1_1/common/include/fsp/memmap.h | 47 +++
.../intel/fsp/fsp1_1/common/include/fsp/ramstage.h | 36 ++
.../intel/fsp/fsp1_1/common/include/fsp/romstage.h | 98 +++++
.../fsp/fsp1_1/common/include/fsp/soc_binding.h | 39 ++
.../intel/fsp/fsp1_1/common/include/fsp/stack.h | 31 ++
.../fsp/fsp1_1/common/include/fsp/uefi_binding.h | 35 ++
.../intel/fsp/fsp1_1/common/include/fsp/util.h | 102 +++++
src/vendorcode/intel/fsp/fsp1_1/common/raminit.c | 320 ++++++++++++++++
src/vendorcode/intel/fsp/fsp1_1/common/ramstage.c | 223 +++++++++++
src/vendorcode/intel/fsp/fsp1_1/common/romstage.c | 420 +++++++++++++++++++++
.../fsp/fsp1_1/common/romstage_after_verstage.S | 48 +++
src/vendorcode/intel/fsp/fsp1_1/common/stack.c | 178 +++++++++
.../intel/fsp/fsp1_1/common/stage_cache.c | 28 ++
src/vendorcode/intel/fsp/fsp1_1/common/vbt.c | 42 +++
src/vendorcode/intel/fsp/fsp1_1/common/verstage.c | 24 ++
src/vendorcode/intel/fsp/fsp2_0/common/Kconfig | 6 +
.../intel/fsp/fsp2_0/common/Makefile.inc | 28 ++
src/vendorcode/intel/fsp/fsp2_0/common/graphics.c | 105 ++++++
.../intel/fsp/fsp2_0/common/hand_off_block.c | 305 +++++++++++++++
.../intel/fsp/fsp2_0/common/include/fsp/api.h | 110 ++++++
.../fsp/fsp2_0/common/include/fsp/info_header.h | 56 +++
.../intel/fsp/fsp2_0/common/include/fsp/util.h | 42 +++
.../intel/fsp/fsp2_0/common/memory_init.c | 73 ++++
src/vendorcode/intel/fsp/fsp2_0/common/notify.c | 40 ++
.../intel/fsp/fsp2_0/common/silicon_init.c | 59 +++
src/vendorcode/intel/fsp/fsp2_0/common/util.c | 138 +++++++
97 files changed, 5737 insertions(+), 5727 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index b656bbf..d7b53cf 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -432,10 +432,11 @@ source "src/superio/*/Kconfig"
comment "Embedded Controllers"
source "src/ec/acpi/Kconfig"
source "src/ec/*/*/Kconfig"
-# FIXME move to vendorcode
-source "src/drivers/intel/fsp1_0/Kconfig"
+# FIXME, move two lines below to src/vendorcode/intel/Kconfig
+source "src/vendorcode/intel/fsp1_0/common/Kconfig"
source "src/southbridge/intel/common/firmware/Kconfig"
+
source "src/vendorcode/*/Kconfig"
source "src/arch/*/Kconfig"
@@ -445,6 +446,7 @@ endmenu
source "src/device/Kconfig"
menu "Generic Drivers"
+# FIXME: convert remaining drivers to */* and remove following line:
source "src/drivers/*/Kconfig"
source "src/drivers/*/*/Kconfig"
endmenu
diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig
deleted file mode 100644
index 6aa8949..0000000
--- a/src/drivers/intel/fsp1_0/Kconfig
+++ /dev/null
@@ -1,127 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2014 Sage Electronic Engineering, LLC.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if PLATFORM_USES_FSP1_0
-
-comment "Intel FSP"
-
-config HAVE_FSP_BIN
- bool "Use Intel Firmware Support Package"
- help
- Select this option to add an Intel FSP binary to
- the resulting coreboot image.
-
- Note: Without this binary, coreboot builds relying on the FSP
- will not boot
-
-config DCACHE_RAM_BASE
- hex
- default 0xfef00000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-if HAVE_FSP_BIN
-
-config FSP_FILE
- string "Intel FSP binary path and filename"
- help
- The path and filename of the Intel FSP binary for this platform.
-
-endif #HAVE_FSP_BIN
-
-config FSP_LOC
- hex "Intel FSP Binary location in CBFS"
- help
- The location in CBFS that the FSP is located. This must match the
- value that is set in the FSP binary. If the FSP needs to be moved,
- rebase the FSP with Intel's BCT (tool).
-
-config ENABLE_FSP_FAST_BOOT
- bool "Enable Fast Boot"
- select ENABLE_MRC_CACHE
- default n
- help
- Enabling this feature will force the MRC data to be cached in NV
- storage to be used for speeding up boot time on future reboots
- and/or power cycles.
-
-config ENABLE_MRC_CACHE
- bool
- default y if HAVE_ACPI_RESUME
- default n
- help
- Enabling this feature will cause MRC data to be cached in NV storage.
- This can either be used for fast boot, or just because the FSP wants
- it to be saved.
-
-config MRC_CACHE_FMAP
- bool "Use MRC Cache in FMAP"
- depends on ENABLE_MRC_CACHE
- default n
- help
- Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
- You must define a region in your FMAP named "RW_MRC_CACHE".
-
-config MRC_CACHE_SIZE
- hex "Fast Boot Data Cache Size"
- default 0x10000
- depends on ENABLE_MRC_CACHE
- depends on !MRC_CACHE_FMAP
- help
- This is the amount of space in NV storage that is reserved for the
- fast boot data cache storage.
-
- WARNING: Because this area will be erased and re-written, the size
- should be a full sector of the flash ROM chip and nothing else should
- be included in CBFS in any sector that the fast boot cache data is in.
-
-config VIRTUAL_ROM_SIZE
- hex "Virtual ROM Size"
- default ROM_SIZE
- depends on ENABLE_MRC_CACHE
- help
- This is used to calculate the offset of the MRC data cache in NV
- Storage for fast boot. If in doubt, leave this set to the default
- which sets the virtual size equal to the ROM size.
-
- Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are
- loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When
- the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
- size is 16 MB.
-
-config CACHE_ROM_SIZE_OVERRIDE
- hex "Cache ROM Size"
- default CBFS_SIZE
- help
- This is the size of the cachable area that is passed into the FSP in
- the early initialization. Typically this should be the size of the CBFS
- area, but the size must be a power of 2 whereas the CBFS size does not
- have this limitation.
-
-config USE_GENERIC_FSP_CAR_INC
- bool
- default n
- help
- The chipset can select this to use a generic cache_as_ram.inc file
- that should be good for all FSP based platforms.
-
-config FSP_USES_UPD
- bool
- default n
- help
- If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
-endif #PLATFORM_USES_FSP1_0
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
deleted file mode 100644
index 4ff1068..0000000
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2014 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-ifeq ($(CONFIG_PLATFORM_USES_FSP1_0),y)
-
-ramstage-y += fsp_util.c hob.c
-romstage-y += fsp_util.c hob.c
-
-ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
-romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
-
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
-
-cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
-
-ifeq ($(CONFIG_HAVE_FSP_BIN),y)
-cbfs-files-y += fsp.bin
-fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
-fsp.bin-position := $(CONFIG_FSP_LOC)
-fsp.bin-type := fsp
-endif
-
-ifeq ($(CONFIG_ENABLE_MRC_CACHE),y)
-ifneq ($(CONFIG_MRC_CACHE_FMAP),y)
-$(obj)/mrc.cache:
- dd if=/dev/zero count=1 \
- bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
- tr '\000' '\377' > $@
-
-cbfs-files-y += mrc.cache
-mrc.cache-file := $(obj)/mrc.cache
-mrc.cache-align := 0x10000
-mrc.cache-type := mrc_cache
-endif
-endif
-
-endif
diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc
deleted file mode 100644
index e79c3c1..0000000
--- a/src/drivers/intel/fsp1_0/cache_as_ram.inc
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
- * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/post_code.h>
-#include <cbmem.h>
-
- cmp $0, %eax
- je cache_as_ram
- mov $0xa0, %eax
- jmp .Lhlt
-
-cache_as_ram:
- post_code(0x20)
-
- /*
- * Find the FSP binary in cbfs.
- * Make a fake stack that has the return value back to this code.
- */
- lea fake_fsp_stack, %esp
- jmp find_fsp
-find_fsp_ret:
- /* Save the FSP location */
- mov %eax, %ebp
- cmp $CONFIG_FSP_LOC, %eax
- jae find_fsp_ok
- mov $0xb0, %eax
- jmp .Lhlt
-
-find_fsp_ok:
- post_code(POST_FSP_TEMP_RAM_INIT)
-
- /* Calculate entry into FSP */
- mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
- add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */
-
- /*
- * Pass early init variables on a fake stack (no memory yet)
- * as well as the return location
- */
- lea CAR_init_stack, %esp
-
- /* call FSP binary to setup temporary stack */
- jmp *%eax
-
-CAR_init_done:
- addl $4, %esp
- cmp $0, %eax
- je car_init_ok
- add $0xc0, %eax
- jmp .Lhlt
-
-car_init_ok:
-
- /* Save FSP_INFO_HEADER location in ebx */
- mov %ebp, %ebx
-
- /*
- * set up bootloader stack
- * ecx: stack base
- * edx: stack top
- */
- mov %edx, %esp
- movl %esp, %ebp
-
- /* Clear the cbmem CAR memory region. */
- movl %ecx, %edi
- movl %edx, %ecx
- sub %edi, %ecx
- shr $2, %ecx
- xorl %eax, %eax
- rep stosl
-
-before_romstage:
- post_code(0x23)
-
- /* Call romstage.c main function. */
- pushl %ebx /* main takes FSP_INFO_HEADER as its argument */
- call main /* does not return */
- movb $0xB8, %ah
- jmp .Lhlt
-
-.Lhlt:
-#if IS_ENABLED(CONFIG_POST_IO)
- outb %al, $CONFIG_POST_IO_PORT
-#endif
- hlt
- jmp .Lhlt
-
-/*
- * esp is set to this location so that the call into and return from the FSP
- * in find_fsp will work.
- */
- .align 4
-fake_fsp_stack:
- .long find_fsp_ret
-
-CAR_init_params:
- .long dummy_microcode
- .long 0
- .long 0xFFFFFFFF - CACHE_ROM_SIZE + 1 /* Firmware Location */
- .long CACHE_ROM_SIZE /* Total Firmware Length */
-
-CAR_init_stack:
- .long CAR_init_done
- .long CAR_init_params
-
-dummy_microcode:
- .long 0
diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c
deleted file mode 100644
index 68150f9..0000000
--- a/src/drivers/intel/fsp1_0/fastboot_cache.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <bootstate.h>
-#include <console/console.h>
-#include <cbfs.h>
-#include <fmap.h>
-#include <ip_checksum.h>
-#include <device/device.h>
-#include <cbmem.h>
-#include <spi-generic.h>
-#include <spi_flash.h>
-#include <lib.h> // hexdump
-#include "fsp_util.h"
-
-/* convert a pointer to flash area into the offset inside the flash */
-static inline u32 to_flash_offset(void *p) {
- return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE);
-}
-
-static struct mrc_data_container *next_mrc_block(
- struct mrc_data_container *mrc_cache)
-{
- /* MRC data blocks are aligned within the region */
- u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size;
- if (mrc_size & (MRC_DATA_ALIGN - 1UL)) {
- mrc_size &= ~(MRC_DATA_ALIGN - 1UL);
- mrc_size += MRC_DATA_ALIGN;
- }
-
- u8 *region_ptr = (u8*)mrc_cache;
- region_ptr += mrc_size;
- return (struct mrc_data_container *)region_ptr;
-}
-
-static int is_mrc_cache(struct mrc_data_container *mrc_cache)
-{
- return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE);
-}
-
-static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
-{
- size_t region_size;
-
- if (IS_ENABLED(CONFIG_MRC_CACHE_FMAP)) {
- struct region_device rdev;
- if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) {
- *mrc_region_ptr = rdev_mmap_full(&rdev);
- return region_device_sz(&rdev);
- }
- *mrc_region_ptr = NULL;
- return 0;
- } else {
- *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache",
- CBFS_TYPE_MRC_CACHE,
- ®ion_size);
-
- return region_size;
- }
-}
-
-/*
- * Find the largest index block in the MRC cache. Return NULL if none is
- * found.
- */
-static struct mrc_data_container *find_current_mrc_cache_local
- (struct mrc_data_container *mrc_cache, u32 region_size)
-{
- u32 region_end;
- u32 entry_id = 0;
- struct mrc_data_container *mrc_next = mrc_cache;
-
- region_end = (u32) mrc_cache + region_size;
-
- /* Search for the last filled entry in the region */
- while (is_mrc_cache(mrc_next)) {
- entry_id++;
- mrc_cache = mrc_next;
- mrc_next = next_mrc_block(mrc_next);
- if ((u32)mrc_next >= region_end) {
- /* Stay in the MRC data region */
- break;
- }
- }
-
- if (entry_id == 0) {
- printk(BIOS_ERR, "%s: No valid fast boot cache found.\n", __func__);
- return NULL;
- }
-
- /* Verify checksum */
- if (mrc_cache->mrc_checksum !=
- compute_ip_checksum(mrc_cache->mrc_data,
- mrc_cache->mrc_data_size)) {
- printk(BIOS_ERR, "%s: fast boot cache checksum mismatch\n", __func__);
- return NULL;
- }
-
- printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__,
- entry_id - 1);
-
- return mrc_cache;
-}
-
-/* SPI code needs malloc/free.
- * Also unknown if writing flash from XIP-flash code is a good idea
- */
-#if !defined(__PRE_RAM__)
-/* find the first empty block in the MRC cache area.
- * If there's none, return NULL.
- *
- * @mrc_cache_base - base address of the MRC cache area
- * @mrc_cache - current entry (for which we need to find next)
- * @region_size - total size of the MRC cache area
- */
-static struct mrc_data_container *find_next_mrc_cache
- (struct mrc_data_container *mrc_cache_base,
- struct mrc_data_container *mrc_cache,
- u32 region_size)
-{
- u32 region_end = (u32) mrc_cache_base + region_size;
- u32 mrc_data_size = mrc_cache->mrc_data_size;
-
- mrc_cache = next_mrc_block(mrc_cache);
- if (((u32)mrc_cache + mrc_data_size) >= region_end) {
- /* Crossed the boundary */
- mrc_cache = NULL;
- printk(BIOS_DEBUG, "%s: no available entries found\n",
- __func__);
- } else {
- printk(BIOS_DEBUG,
- "%s: picked next entry from cache block at %p\n",
- __func__, mrc_cache);
- }
-
- return mrc_cache;
-}
-
-void update_mrc_cache(void *unused)
-{
- printk(BIOS_DEBUG, "Updating fast boot cache data.\n");
- struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA);
- struct mrc_data_container *cache, *cache_base;
- u32 cache_size;
-
- if (!current) {
- printk(BIOS_ERR, "No fast boot cache in cbmem. Can't update flash.\n");
- return;
- }
- if (current->mrc_data_size == -1) {
- printk(BIOS_ERR, "Fast boot cache data in cbmem invalid.\n");
- return;
- }
-
- cache_size = get_mrc_cache_region(&cache_base);
- if (cache_base == NULL) {
- printk(BIOS_ERR, "%s: could not find fast boot cache area\n",
- __func__);
- return;
- }
-
- /*
- * we need to:
- * 0. compare MRC data to last mrc-cache block (exit if same)
- */
- cache = find_current_mrc_cache_local(cache_base, cache_size);
-
- if (cache && (cache->mrc_data_size == current->mrc_data_size) &&
- (memcmp(cache, current, cache->mrc_data_size) == 0)) {
- printk(BIOS_DEBUG,
- "MRC data in flash is up to date. No update.\n");
- return;
- }
-
- /* 1. use spi_flash_probe() to find the flash, then... */
- spi_init();
- struct spi_flash *flash = spi_flash_probe(0, 0);
- if (!flash) {
- printk(BIOS_DEBUG, "Could not find SPI device\n");
- return;
- }
-
- /* 2. look up the first unused block */
- if (cache)
- cache = find_next_mrc_cache(cache_base, cache, cache_size);
-
- /*
- * 3. if no such place exists, erase entire mrc-cache range & use
- * block 0. First time around the erase is not needed, but this is a
- * small overhead for simpler code.
- */
- if (!cache) {
- printk(BIOS_DEBUG,
- "Need to erase the MRC cache region of %d bytes at %p\n",
- cache_size, cache_base);
-
- flash->erase(flash, to_flash_offset(cache_base), cache_size);
-
- /* we will start at the beginning again */
- cache = cache_base;
- }
- /* 4. write mrc data with flash->write() */
- printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n",
- cache);
- flash->write(flash, to_flash_offset(cache),
- current->mrc_data_size + sizeof(*current), current);
-}
-
-#endif /* !defined(__PRE_RAM__) */
-
-void * find_and_set_fastboot_cache(void)
-{
- struct mrc_data_container *mrc_cache = NULL;
- if (((mrc_cache = find_current_mrc_cache()) == NULL) ||
- (mrc_cache->mrc_data_size == -1UL)) {
- printk(BIOS_DEBUG, "FSP MRC cache not present.\n");
- return NULL;
- }
- printk(BIOS_DEBUG, "FSP MRC cache present at %x.\n", (u32)mrc_cache);
- printk(BIOS_SPEW, "Saved MRC data:\n");
- hexdump32(BIOS_SPEW, (void *)mrc_cache->mrc_data, (mrc_cache->mrc_data_size) / 4);
- return (void *) mrc_cache->mrc_data;
-}
-
-struct mrc_data_container *find_current_mrc_cache(void)
-{
- struct mrc_data_container *cache_base;
- u32 cache_size;
-
- cache_size = get_mrc_cache_region(&cache_base);
- if (cache_base == NULL) {
- printk(BIOS_ERR, "%s: could not find fast boot cache area\n",
- __func__);
- return NULL;
- }
-
- /*
- * we need to:
- * 0. compare MRC data to last mrc-cache block (exit if same)
- */
- return find_current_mrc_cache_local(cache_base, cache_size);
-}
diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c
deleted file mode 100644
index a3fef2d..0000000
--- a/src/drivers/intel/fsp1_0/fsp_util.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <console/console.h>
-#include <bootstate.h>
-#include <cbmem.h>
-#include "fsp_util.h"
-#include <lib.h> // hexdump
-#include <ip_checksum.h>
-#include <timestamp.h>
-
-#ifndef __PRE_RAM__
-/* Globals pointers for FSP structures */
-void *FspHobListPtr = NULL;
-FSP_INFO_HEADER *fsp_header_ptr = NULL;
-
-void FspNotify (u32 Phase)
-{
- FSP_NOTFY_PHASE NotifyPhaseProc;
- NOTIFY_PHASE_PARAMS NotifyPhaseParams;
- EFI_STATUS Status;
-
- if (fsp_header_ptr == NULL) {
- fsp_header_ptr = (void *)find_fsp();
- if ((u32)fsp_header_ptr < 0xff) {
- post_code(0x4F); /* output something in case there is no serial */
- die("Can't find the FSP!\n");
- }
- }
-
- /* call FSP PEI to Notify PostPciEnumeration */
- NotifyPhaseProc = (FSP_NOTFY_PHASE)(fsp_header_ptr->ImageBase +
- fsp_header_ptr->NotifyPhaseEntry);
- NotifyPhaseParams.Phase = Phase;
-
- timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ?
- TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE);
-
- Status = NotifyPhaseProc (&NotifyPhaseParams);
-
- timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ?
- TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE);
-
- if (Status != 0)
- printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status);
-}
-#endif /* #ifndef __PRE_RAM__ */
-
-#ifdef __PRE_RAM__
-
-/*
- * Call the FSP to do memory init. The FSP doesn't return to this function.
- * The FSP returns to the romstage_main_continue().
- */
-void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
-{
- FSP_FSP_INIT FspInitApi;
- FSP_INIT_PARAMS FspInitParams;
- FSP_INIT_RT_BUFFER FspRtBuffer;
-#if IS_ENABLED(CONFIG_FSP_USES_UPD)
- UPD_DATA_REGION fsp_upd_data;
-#endif
-
- memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));
- FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP;
- FspInitParams.NvsBufferPtr = NULL;
-
-#if IS_ENABLED(CONFIG_FSP_USES_UPD)
- FspRtBuffer.Common.UpdDataRgnPtr = &fsp_upd_data;
-#endif
- FspInitParams.RtBufferPtr = (FSP_INIT_RT_BUFFER *)&FspRtBuffer;
- FspInitParams.ContinuationFunc = (CONTINUATION_PROC)ChipsetFspReturnPoint;
- FspInitApi = (FSP_FSP_INIT)(fsp_ptr->ImageBase + fsp_ptr->FspInitEntry);
-
- /* Call the chipset code to fill in the chipset specific structures */
- chipset_fsp_early_init(&FspInitParams, fsp_ptr);
-
- /* Call back to romstage for board specific changes */
- romstage_fsp_rt_buffer_callback(&FspRtBuffer);
-
- post_code(POST_FSP_MEMORY_INIT);
- FspInitApi(&FspInitParams);
-
- /* Should never return. Control will continue from ContinuationFunc */
- die("Uh Oh! FspInitApi returned");
-}
-#endif /* __PRE_RAM__ */
-
-volatile u8 * find_fsp ()
-{
-
-#ifdef __PRE_RAM__
- volatile register u8 *fsp_ptr asm ("eax");
-
- /* Entry point for CAR assembly routine */
- __asm__ __volatile__ (
- ".global find_fsp\n\t"
- "find_fsp:\n\t"
- );
-#else
- volatile u8 *fsp_ptr;
-#endif /* __PRE_RAM__ */
-
- /* The FSP is stored in CBFS */
- fsp_ptr = (u8 *) CONFIG_FSP_LOC;
-
- /* Check the FV signature, _FVH */
- if (((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->Signature == 0x4856465F) {
- /* Go to the end of the FV header and align the address. */
- fsp_ptr += ((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->ExtHeaderOffset;
- fsp_ptr += ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)fsp_ptr)->ExtHeaderSize;
- fsp_ptr = (u8 *)(((u32)fsp_ptr + 7) & 0xFFFFFFF8);
- } else {
- fsp_ptr = (u8*)ERROR_NO_FV_SIG;
- }
-
- /* Check the FFS GUID */
- if (((u32)fsp_ptr > 0xff) &&
- (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[0] == 0x912740BE) &&
- (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[1] == 0x47342284) &&
- (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[2] == 0xB08471B9) &&
- (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[3] == 0x0C3F3527)) {
- /* Add the FFS Header size to the base to find the Raw section Header */
- fsp_ptr += sizeof(EFI_FFS_FILE_HEADER);
- } else {
- fsp_ptr = (u8 *)ERROR_NO_FFS_GUID;
- }
-
- if (((u32)fsp_ptr > 0xff) &&
- ((EFI_RAW_SECTION *)fsp_ptr)->Type == EFI_SECTION_RAW) {
- /* Add the Raw Header size to the base to find the FSP INFO Header */
- fsp_ptr += sizeof(EFI_RAW_SECTION);
- } else {
- fsp_ptr = (u8 *)ERROR_NO_INFO_HEADER;
- }
-
- /* Verify that the FSP is set to the base address we're expecting.*/
- if (((u32)fsp_ptr > 0xff) &&
- (*(u32*)(fsp_ptr + FSP_IMAGE_BASE_LOC) != CONFIG_FSP_LOC)) {
- fsp_ptr = (u8 *)ERROR_IMAGEBASE_MISMATCH;
- }
-
- /* Verify the FSP Signature */
- if (((u32)fsp_ptr > 0xff) &&
- (*(u32*)(fsp_ptr + FSP_IMAGE_SIG_LOC) != FSP_SIG)){
- fsp_ptr = (u8 *)ERROR_INFO_HEAD_SIG_MISMATCH;
- }
-
- /* Verify the FSP ID */
- if (((u32)fsp_ptr > 0xff) &&
- ((*(u32 *)(fsp_ptr + FSP_IMAGE_ID_LOC) != FSP_IMAGE_ID_DWORD0) ||
- (*(u32 *)(fsp_ptr + (FSP_IMAGE_ID_LOC + 4)) != FSP_IMAGE_ID_DWORD1))) {
- fsp_ptr = (u8 *)ERROR_FSP_SIG_MISMATCH;
- }
-
- return (fsp_ptr);
-}
-
-/** finds the saved temporary memory information in the FSP HOB list
- *
- * @param hob_list_ptr pointer to the start of the hob list
- * @return pointer to saved CAR MEM or NULL if not found.
- */
-void * find_saved_temp_mem(void *hob_list_ptr)
-{
- EFI_GUID temp_hob_guid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID;
- EFI_HOB_GUID_TYPE *saved_mem_hob =
- (EFI_HOB_GUID_TYPE *) find_hob_by_guid(
- hob_list_ptr, &temp_hob_guid);
-
- if (saved_mem_hob == NULL)
- return NULL;
-
- return (void *) ((char *) saved_mem_hob + sizeof(EFI_HOB_GUID_TYPE));
-}
-
-#ifndef FSP_RESERVE_MEMORY_SIZE
-/** @brief locates the HOB containing the location of the fsp reserved mem area
- *
- * @param hob_list_ptr pointer to the start of the hob list
- * @return pointer to the start of the FSP reserved memory or NULL if not found.
- */
-void * find_fsp_reserved_mem(void *hob_list_ptr)
-{
- EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
- EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem =
- (EFI_HOB_RESOURCE_DESCRIPTOR *) find_hob_by_guid(
- hob_list_ptr, &fsp_reserved_guid);
-
- if (fsp_reserved_mem == NULL)
- return NULL;
-
- return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart);
-}
-#endif /* FSP_RESERVE_MEMORY_SIZE */
-
-#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */
-
-void print_fsp_info(void) {
-
- if (fsp_header_ptr == NULL)
- fsp_header_ptr = (void *)find_fsp();
-
- if ((u32)fsp_header_ptr < 0xff) {
- post_code(0x4F); /* post code in case there is no serial */
- die("Can't find the FSP!\n");
- }
-
- if (FspHobListPtr == NULL) {
- FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));
- }
-
- printk(BIOS_SPEW,"fsp_header_ptr: %p\n", fsp_header_ptr);
- printk(BIOS_INFO,"FSP Header Version: %d\n", fsp_header_ptr->HeaderRevision);
- printk(BIOS_INFO,"FSP Revision: %d.%d\n",
- (u8)((fsp_header_ptr->ImageRevision >> 8) & 0xff),
- (u8)(fsp_header_ptr->ImageRevision & 0xff));
-}
-
-
-#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
-/**
- * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM
- */
-int save_mrc_data(void *hob_start)
-{
- u32 *mrc_hob;
- u32 *mrc_hob_data;
- u32 mrc_hob_size;
- struct mrc_data_container *mrc_data;
- int output_len;
- const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
-
- mrc_hob = GetNextGuidHob(&mrc_guid, hob_start);
- if (mrc_hob == NULL){
- printk(BIOS_DEBUG, "Memory Configure Data Hob is not present\n");
- return(0);
- }
-
- mrc_hob_data = GET_GUID_HOB_DATA (mrc_hob);
- mrc_hob_size = (u32) GET_HOB_LENGTH(mrc_hob);
-
- printk(BIOS_DEBUG, "Memory Configure Data Hob at %p (size = 0x%x).\n",
- (void *)mrc_hob_data, mrc_hob_size);
-
- output_len = ALIGN(mrc_hob_size, 16);
-
- /* Save the MRC S3/fast boot/ADR restore data to cbmem */
- mrc_data = cbmem_add (CBMEM_ID_MRCDATA,
- output_len + sizeof(struct mrc_data_container));
-
- /* Just return if there was a problem with getting CBMEM */
- if (mrc_data == NULL) {
- printk(BIOS_WARNING, "CBMEM was not available to save the fast boot cache data.\n");
- return 0;
- }
-
- printk(BIOS_DEBUG, "Copy FSP MRC DATA to HOB (source addr %p, dest addr %p, %u bytes)\n",
- (void *)mrc_hob_data, mrc_data, output_len);
-
- mrc_data->mrc_signature = MRC_DATA_SIGNATURE;
- mrc_data->mrc_data_size = output_len;
- mrc_data->reserved = 0;
- memcpy(mrc_data->mrc_data, (const void *)mrc_hob_data, mrc_hob_size);
-
- /* Zero the unused space in aligned buffer. */
- if (output_len > mrc_hob_size)
- memset((mrc_data->mrc_data + mrc_hob_size), 0,
- output_len - mrc_hob_size);
-
- mrc_data->mrc_checksum = compute_ip_checksum(mrc_data->mrc_data,
- mrc_data->mrc_data_size);
-
- printk(BIOS_SPEW, "Fast boot data (includes align and checksum):\n");
- hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4);
- return (1);
-}
-#endif /* CONFIG_ENABLE_MRC_CACHE */
-
-static void find_fsp_hob_update_mrc(void *unused)
-{
- /* Set the global HOB list pointer */
- FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));
-
- if (!FspHobListPtr){
- printk(BIOS_ERR, "ERROR: Could not find FSP HOB pointer in CBFS!\n");
- } else {
- /* 0x0000: Print all types */
- print_hob_type_structure(0x000, FspHobListPtr);
-
- #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
- if(save_mrc_data(FspHobListPtr))
- update_mrc_cache(NULL);
- else
- printk(BIOS_DEBUG,"Not updating MRC data in flash.\n");
- #endif
- }
-}
-
-/** @brief Notify FSP for PostPciEnumeration
- *
- * @param unused
- */
-static void fsp_after_pci_enum(void *unused)
-{
- /* This call needs to be done before resource allocation. */
- printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
- post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
- FspNotify(EnumInitPhaseAfterPciEnumeration);
- printk(BIOS_DEBUG,
- "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
-}
-
-/** @brief Notify FSP for ReadyToBoot
- *
- * @param unused
- */
-static void fsp_finalize(void *unused)
-{
- printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n");
- print_fsp_info();
- post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
- FspNotify(EnumInitPhaseReadyToBoot);
- printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n");
-}
-
-/* Set up for the ramstage FSP calls */
-BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL);
-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL);
-
-/* Update the MRC/fast boot cache as part of the late table writing stage */
-BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
- find_fsp_hob_update_mrc, NULL);
-#endif /* #ifndef __PRE_RAM__ */
diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h
deleted file mode 100644
index bbdd4de..0000000
--- a/src/drivers/intel/fsp1_0/fsp_util.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef FSP_UTIL_H
-#define FSP_UTIL_H
-
-#include <chipset_fsp_util.h>
-#include "fsp_values.h"
-
-#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
-int save_mrc_data(void *hob_start);
-void * find_and_set_fastboot_cache(void);
-#endif
-
-volatile u8 * find_fsp (void);
-void fsp_early_init(FSP_INFO_HEADER *fsp_info);
-void FspNotify(u32 Phase);
-void FspNotifyReturnPoint(EFI_STATUS Status, VOID *HobListPtr);
-void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer);
-void print_fsp_info(void);
-void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams,
- FSP_INFO_HEADER *fsp_ptr);
-void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr);
-void * find_saved_temp_mem(void *hob_list_ptr);
-void * find_fsp_reserved_mem(void *hob_list_ptr);
-
-/* functions in hob.c */
-void print_hob_mem_attributes(void *Hobptr);
-void print_hob_type_structure(u16 Hobtype, void *Hoblistptr);
-void print_hob_resource_attributes(void *Hobptr);
-void print_guid_type_attributes(void *Hobptr);
-const char * get_hob_type_string(void *Hobptr);
-void * find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1);
-uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2);
-void printguid(EFI_GUID *guid);
-
-/* Additional HOB types not included in the FSP:
- * #define EFI_HOB_TYPE_HANDOFF 0x0001
- * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
- * #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
- * #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
- * #define EFI_HOB_TYPE_FV 0x0005
- * #define EFI_HOB_TYPE_CPU 0x0006
- * #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
- * #define EFI_HOB_TYPE_CV 0x0008
- * #define EFI_HOB_TYPE_UNUSED 0xFFFE
- * #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff
- */
-#define EFI_HOB_TYPE_HANDOFF 0x0001
-#define EFI_HOB_TYPE_MEMORY_POOL 0x0007
-
-#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
-#define MRC_DATA_ALIGN 0x1000
-#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
-
-struct mrc_data_container {
- u32 mrc_signature; // "MRCD"
- u32 mrc_data_size; // Actual total size of this structure
- u32 mrc_checksum; // IP style checksum
- u32 reserved; // For header alignment
- u8 mrc_data[0]; // Variable size, platform/run time dependent.
-} __attribute__ ((packed));
-
-struct mrc_data_container *find_current_mrc_cache(void);
-
-#if !defined(__PRE_RAM__)
-void update_mrc_cache(void *unused);
-#endif
-
-#endif
-
-/* The offset in bytes from the start of the info structure */
-#define FSP_IMAGE_SIG_LOC 0
-#define FSP_IMAGE_ID_LOC 16
-#define FSP_IMAGE_BASE_LOC 28
-
-#define FSP_SIG 0x48505346 /* 'FSPH' */
-
-#define ERROR_NO_FV_SIG 1
-#define ERROR_NO_FFS_GUID 2
-#define ERROR_NO_INFO_HEADER 3
-#define ERROR_IMAGEBASE_MISMATCH 4
-#define ERROR_INFO_HEAD_SIG_MISMATCH 5
-#define ERROR_FSP_SIG_MISMATCH 6
-
-#ifndef __PRE_RAM__
-extern void *FspHobListPtr;
-#endif
-
-#define UPD_DEFAULT_CHECK(member) \
- if (config->member != UPD_DEFAULT) { \
- UpdData->member = config->member - 1; \
- } \
- printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \
- config->member ? "(set)" : "(default)");
-
-#define UPD_SPD_CHECK(member) \
- if (config->member == UPD_SPD_ADDR_DISABLED) { \
- UpdData->member = 0x00; \
- } else if (config->member != UPD_SPD_ADDR_DEFAULT) { \
- UpdData->member = config->member; \
- } \
- printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \
- config->member ? "(set)" : "(default)");
-
-#define UPD_DEVICE_CHECK(devicename, member, statement) \
- case devicename: \
- UpdData->member = dev->enabled; \
- printk(FSP_INFO_LEVEL, statement "%s\n", \
- UpdData->member?"Enabled":"Disabled"); \
- break;
-
-
-#ifndef FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID
-#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \
- { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } };
-#endif
-
-#endif /* FSP_UTIL_H */
diff --git a/src/drivers/intel/fsp1_0/fsp_values.h b/src/drivers/intel/fsp1_0/fsp_values.h
deleted file mode 100644
index 337e751..0000000
--- a/src/drivers/intel/fsp1_0/fsp_values.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef FSP_VALUES_H
-#define FSP_VALUES_H
-
-#ifndef FSP_DEBUG_LEVEL
-# define FSP_DEBUG_LEVEL BIOS_SPEW
-#endif
-
-#ifndef FSP_INFO_LEVEL
-# define FSP_INFO_LEVEL BIOS_DEBUG
-#endif
-
-#define INCREMENT_FOR_DEFAULT(x) (x+1)
-
-#define UPD_DEFAULT 0x00
-#define UPD_DISABLE INCREMENT_FOR_DEFAULT(0)
-#define UPD_ENABLE INCREMENT_FOR_DEFAULT(1)
-#define UPD_USE_DEVICETREE 0xff
-
-#define UPD_SPD_ADDR_DEFAULT UPD_DEFAULT
-#define UPD_SPD_ADDR_DISABLED 0xFF
-
-#endif
diff --git a/src/drivers/intel/fsp1_0/hob.c b/src/drivers/intel/fsp1_0/hob.c
deleted file mode 100644
index 4aac147..0000000
--- a/src/drivers/intel/fsp1_0/hob.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <console/console.h>
-#include <lib.h> // hexdump
-#include "fsp_util.h"
-
-
-/** Displays a GUID's address and value
- *
- * @param guid pointer to the GUID to display
- */
-void printguid(EFI_GUID *guid)
-{
- printk(BIOS_SPEW,"Address: %p Guid: %08lx-%04x-%04x-",
- guid, (unsigned long)guid->Data1,
- guid->Data2, guid->Data3);
- printk(BIOS_SPEW,"%02x%02x%02x%02x%02x%02x%02x%02x\n",
- guid->Data4[0], guid->Data4[1],
- guid->Data4[2], guid->Data4[3],
- guid->Data4[4], guid->Data4[5],
- guid->Data4[6], guid->Data4[7] );
-}
-
-void print_hob_mem_attributes(void *Hobptr)
-{
- EFI_HOB_MEMORY_ALLOCATION *HobMemoryPtr = (EFI_HOB_MEMORY_ALLOCATION *)Hobptr;
- EFI_MEMORY_TYPE Hobmemtype = HobMemoryPtr->AllocDescriptor.MemoryType;
- u64 Hobmemaddr = HobMemoryPtr->AllocDescriptor.MemoryBaseAddress;
- u64 Hobmemlength = HobMemoryPtr->AllocDescriptor.MemoryLength;
- const char * Hobmemtypenames[15];
-
- Hobmemtypenames[0] = "EfiReservedMemoryType";
- Hobmemtypenames[1] = "EfiLoaderCode";
- Hobmemtypenames[2] = "EfiLoaderData";
- Hobmemtypenames[3] = "EfiBootServicesCode";
- Hobmemtypenames[4] = "EfiBootServicesData";
- Hobmemtypenames[5] = "EfiRuntimeServicesCode";
- Hobmemtypenames[6] = "EfiRuntimeServicesData";
- Hobmemtypenames[7] = "EfiConventionalMemory";
- Hobmemtypenames[8] = "EfiUnusableMemory";
- Hobmemtypenames[9] = "EfiACPIReclaimMemory";
- Hobmemtypenames[10] = "EfiACPIMemoryNVS";
- Hobmemtypenames[11] = "EfiMemoryMappedIO";
- Hobmemtypenames[12] = "EfiMemoryMappedIOPortSpace";
- Hobmemtypenames[13] = "EfiPalCode";
- Hobmemtypenames[14] = "EfiMaxMemoryType";
-
- printk(BIOS_SPEW, " Memory type %s (0x%x)\n",
- Hobmemtypenames[(u32)Hobmemtype], (u32) Hobmemtype);
- printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n",
- (unsigned long)Hobmemaddr, (unsigned long)Hobmemlength);
-}
-
-void print_hob_resource_attributes(void *Hobptr)
-{
- EFI_HOB_RESOURCE_DESCRIPTOR *HobResourcePtr =
- (EFI_HOB_RESOURCE_DESCRIPTOR *)Hobptr;
- u32 Hobrestype = HobResourcePtr->ResourceType;
- u32 Hobresattr = HobResourcePtr->ResourceAttribute;
- u64 Hobresaddr = HobResourcePtr->PhysicalStart;
- u64 Hobreslength = HobResourcePtr->ResourceLength;
- const char *Hobrestypestr = NULL;
-
- // HOB Resource Types
- switch (Hobrestype) {
- case EFI_RESOURCE_SYSTEM_MEMORY:
- Hobrestypestr = "EFI_RESOURCE_SYSTEM_MEMORY"; break;
- case EFI_RESOURCE_MEMORY_MAPPED_IO:
- Hobrestypestr = "EFI_RESOURCE_MEMORY_MAPPED_IO"; break;
- case EFI_RESOURCE_IO:
- Hobrestypestr = "EFI_RESOURCE_IO"; break;
- case EFI_RESOURCE_FIRMWARE_DEVICE:
- Hobrestypestr = "EFI_RESOURCE_FIRMWARE_DEVICE"; break;
- case EFI_RESOURCE_MEMORY_MAPPED_IO_PORT:
- Hobrestypestr = "EFI_RESOURCE_MEMORY_MAPPED_IO_PORT"; break;
- case EFI_RESOURCE_MEMORY_RESERVED:
- Hobrestypestr = "EFI_RESOURCE_MEMORY_RESERVED"; break;
- case EFI_RESOURCE_IO_RESERVED:
- Hobrestypestr = "EFI_RESOURCE_IO_RESERVED"; break;
- case EFI_RESOURCE_MAX_MEMORY_TYPE:
- Hobrestypestr = "EFI_RESOURCE_MAX_MEMORY_TYPE"; break;
- default:
- Hobrestypestr = "EFI_RESOURCE_UNKNOWN"; break;
- }
-
- printk(BIOS_SPEW, " Resource %s (0x%0x) has attributes 0x%0x\n",
- Hobrestypestr, Hobrestype, Hobresattr);
- printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n",
- (unsigned long)Hobresaddr, (unsigned long)Hobreslength);
-}
-
-const char * get_hob_type_string(void *Hobptr)
-{
- EFI_HOB_GENERIC_HEADER *HobHeaderPtr = (EFI_HOB_GENERIC_HEADER *)Hobptr;
- u16 Hobtype = HobHeaderPtr->HobType;
- const char *Hobtypestring = NULL;
-
- switch (Hobtype) {
- case EFI_HOB_TYPE_HANDOFF:
- Hobtypestring = "EFI_HOB_TYPE_HANDOFF"; break;
- case EFI_HOB_TYPE_MEMORY_ALLOCATION:
- Hobtypestring = "EFI_HOB_TYPE_MEMORY_ALLOCATION"; break;
- case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
- Hobtypestring = "EFI_HOB_TYPE_RESOURCE_DESCRIPTOR"; break;
- case EFI_HOB_TYPE_GUID_EXTENSION:
- Hobtypestring = "EFI_HOB_TYPE_GUID_EXTENSION"; break;
- case EFI_HOB_TYPE_MEMORY_POOL:
- Hobtypestring = "EFI_HOB_TYPE_MEMORY_POOL"; break;
- case EFI_HOB_TYPE_UNUSED:
- Hobtypestring = "EFI_HOB_TYPE_UNUSED"; break;
- case EFI_HOB_TYPE_END_OF_HOB_LIST:
- Hobtypestring = "EFI_HOB_TYPE_END_OF_HOB_LIST"; break;
- default:
- Hobtypestring = "EFI_HOB_TYPE_UNRECOGNIZED"; break;
- }
-
- return Hobtypestring;
-}
-
-/** Displays the length, location, and GUID value of a GUID extension
- *
- * The EFI_HOB_GUID_TYPE is very basic - it just contains the standard
- * HOB header containing the HOB type and length, and a GUID for
- * identification. The rest of the data is undefined and must be known
- * based on the GUID.
- *
- * This displays the entire HOB length, and the location of the start
- * of the HOB, *NOT* the length of or the start of the data inside the HOB.
- *
- * @param Hobptr
- */
-void print_guid_type_attributes(void *Hobptr)
-{
- printk(BIOS_SPEW, " at location %p with length0x%0lx\n ",
- Hobptr, (unsigned long)(((EFI_PEI_HOB_POINTERS *) \
- Hobptr)->Guid->Header.HobLength));
- printguid(&(((EFI_HOB_GUID_TYPE *)Hobptr)->Name));
-
-}
-
-/* Print out a structure of all the HOBs
- * that match a certain type:
- * Print all types (0x0000)
- * EFI_HOB_TYPE_HANDOFF (0x0001)
- * EFI_HOB_TYPE_MEMORY_ALLOCATION (0x0002)
- * EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (0x0003)
- * EFI_HOB_TYPE_GUID_EXTENSION (0x0004)
- * EFI_HOB_TYPE_MEMORY_POOL (0x0007)
- * EFI_HOB_TYPE_UNUSED (0xFFFE)
- * EFI_HOB_TYPE_END_OF_HOB_LIST (0xFFFF)
- */
-void print_hob_type_structure(u16 Hobtype, void *Hoblistptr)
-{
- u32 *Currenthob;
- u32 *Nexthob = 0;
- u8 Lasthob = 0;
- u32 Currenttype;
- const char *Currenttypestr;
-
- Currenthob = Hoblistptr;
-
- /* Print out HOBs of our desired type until
- * the end of the HOB list
- */
- printk(BIOS_DEBUG, "\n=== FSP HOB Data Structure ===\n");
- printk(BIOS_DEBUG, "FSP Hoblistptr: 0x%0x\n",
- (u32) Hoblistptr);
- do {
- EFI_HOB_GENERIC_HEADER *CurrentHeaderPtr =
- (EFI_HOB_GENERIC_HEADER *)Currenthob;
- Currenttype = CurrentHeaderPtr->HobType; /* Get the type of this HOB */
- Currenttypestr = get_hob_type_string(Currenthob);
-
- if (Currenttype == Hobtype || Hobtype == 0x0000) {
- printk(BIOS_DEBUG, "HOB 0x%0x is an %s (type 0x%0x)\n",
- (u32) Currenthob, Currenttypestr, Currenttype);
- switch (Currenttype) {
- case EFI_HOB_TYPE_MEMORY_ALLOCATION:
- print_hob_mem_attributes(Currenthob); break;
- case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
- print_hob_resource_attributes(Currenthob); break;
- case EFI_HOB_TYPE_GUID_EXTENSION:
- print_guid_type_attributes(Currenthob); break;
- }
- }
-
- Lasthob = END_OF_HOB_LIST(Currenthob); /* Check for end of HOB list */
- if (!Lasthob) {
- Nexthob = GET_NEXT_HOB(Currenthob); /* Get next HOB pointer */
- Currenthob = Nexthob; // Start on next HOB
- }
- } while (!Lasthob);
- printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n");
-}
-
-
-/** Finds a HOB entry based on type and guid
- *
- * @param current_hob pointer to the start of the HOB list
- * @param guid the GUID of the HOB entry to find
- * @return pointer to the start of the requested HOB or NULL if not found.
- */
-void * find_hob_by_guid(void *current_hob, EFI_GUID *guid)
-{
- do {
- switch (((EFI_HOB_GENERIC_HEADER *)current_hob)->HobType) {
-
- case EFI_HOB_TYPE_MEMORY_ALLOCATION:
- if (guids_are_equal(guid, &(((EFI_HOB_MEMORY_ALLOCATION *) \
- current_hob)->AllocDescriptor.Name)))
- return current_hob;
- break;
- case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
- if (guids_are_equal(guid,
- &(((EFI_HOB_RESOURCE_DESCRIPTOR *) \
- current_hob)->Owner)))
- return current_hob;
- break;
- case EFI_HOB_TYPE_GUID_EXTENSION:
- if (guids_are_equal(guid, &(((EFI_HOB_GUID_TYPE *) \
- current_hob)->Name)))
- return current_hob;
- break;
- }
-
- if (!END_OF_HOB_LIST(current_hob))
- current_hob = GET_NEXT_HOB(current_hob); /* Get next HOB pointer */
- } while (!END_OF_HOB_LIST(current_hob));
-
- return NULL;
-}
-
-/** Compares a pair of GUIDs to see if they are equal
- *
- * GUIDs are 128 bits long, so compare them as pairs of quadwords.
- *
- * @param guid1 pointer to the first of the GUIDs to compare
- * @param guid2 pointer to the second of the GUIDs to compare
- * @return 1 if the GUIDs were equal, 0 if GUIDs were not equal
- */
-uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2)
-{
- uint64_t* guid_1 = (void *) guid1;
- uint64_t* guid_2 = (void *) guid2;
-
- if ((*(guid_1) != *(guid_2)) || (*(guid_1 + 1) != *(guid_2 + 1)))
- return 0;
-
- return 1;
-}
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
deleted file mode 100644
index 9b2c463..0000000
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ /dev/null
@@ -1,118 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2014 Sage Electronic Engineering, LLC.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config PLATFORM_USES_FSP1_1
- bool
- select UEFI_2_4_BINDING
- help
- Does the code require the Intel Firmware Support Package?
-
-if PLATFORM_USES_FSP1_1
-
-comment "Intel FSP 1.1"
-
-config HAVE_FSP_BIN
- bool "Should the Intel FSP binary be added to the flash image"
- help
- Select this option to add an Intel FSP binary to
- the resulting coreboot image.
-
- Note: Without this binary, coreboot builds relying on the FSP
- will not boot
-
-config CPU_MICROCODE_CBFS_LEN
- hex "Microcode update region length in bytes"
- default 0
- help
- The length in bytes of the microcode update region.
-
-config CPU_MICROCODE_CBFS_LOC
- hex "Microcode update base address in CBFS"
- default 0
- help
- The location (base address) in CBFS that contains the microcode update
- binary.
-
-config FSP_FILE
- string "Intel FSP binary path and filename"
- help
- The path and filename of the Intel FSP binary for this platform.
-
-config FSP_IMAGE_ID_STRING
- string "8 byte platform string identifying the FSP platform"
- default "$XXXFSP$"
- help
- 8 ASCII character byte signature string that will help match the FSP
- binary to a supported hardware configuration.
-
-config FSP_LOC
- hex "Intel FSP Binary location in CBFS"
- default 0xffee0000
- help
- The location in CBFS that the FSP is located. This must match the
- value that is set in the FSP binary. If the FSP needs to be moved,
- rebase the FSP with Intel's BCT (tool).
-
-config DISPLAY_FAST_BOOT_DATA
- bool "Display fast boot data"
- default n
-
-config DISPLAY_HOBS
- bool "Display hand-off-blocks (HOBs)"
- default n
-
-config DISPLAY_VBT
- bool "Display Video BIOS Table (VBT)"
- default n
-
-config DISPLAY_FSP_ENTRY_POINTS
- bool "Display FSP entry points"
- default n
-
-config DISPLAY_UPD_DATA
- bool "Display UPD data"
- default n
- help
- Display the user specified product data prior to memory
- initialization.
-
-config FSP_USES_UPD
- bool
- default n
- help
- If this FSP uses UPD/VPD data regions, select this in the chipset
- Kconfig.
-
-config GOP_SUPPORT
- bool "Enable GOP support"
- default n
-
-config ROMSTAGE_RAM_STACK_SIZE
- hex "Size of the romstage RAM stack in bytes"
- default 0x5000
-
-config USE_GENERIC_FSP_CAR_INC
- bool
- default n
- help
- The chipset can select this to use a generic cache_as_ram.inc file
- that should be good for all FSP based platforms.
-
-config VBT_FILE
- string "GOP Video BIOS table binary path"
- depends on GOP_SUPPORT
- default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin"
-
-endif #PLATFORM_USES_FSP1_1
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
deleted file mode 100644
index 3f214cb..0000000
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ /dev/null
@@ -1,59 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2014 Sage Electronic Engineering, LLC.
-# Copyright (C) 2015 Intel Corp.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
-
-verstage-y += car.c
-verstage-y += fsp_util.c
-verstage-y += verstage.c
-
-romstage-y += car.c
-romstage-y += fsp_util.c
-romstage-y += hob.c
-romstage-y += raminit.c
-romstage-y += romstage.c
-romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
-romstage-y += stack.c
-romstage-y += stage_cache.c
-
-ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
-ramstage-y += fsp_relocate.c
-ramstage-y += fsp_util.c
-ramstage-y += hob.c
-ramstage-y += ramstage.c
-ramstage-y += stage_cache.c
-ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
-
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
-
-cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
-
-
-# Add the GOP Video BIOS Table to the cbfs image
-cbfs-files-$(CONFIG_GOP_SUPPORT) += vbt.bin
-vbt.bin-file := $(call strip_quotes,$(CONFIG_VBT_FILE))
-vbt.bin-type := optionrom
-
-
-# Add the FSP binary to the cbfs image
-ifeq ($(CONFIG_HAVE_FSP_BIN),y)
-cbfs-files-y += fsp.bin
-fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
-fsp.bin-position := $(CONFIG_FSP_LOC)
-fsp.bin-type := fsp
-endif
-
-endif
diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S
deleted file mode 100644
index 122c0bf..0000000
--- a/src/drivers/intel/fsp1_1/after_raminit.S
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
- * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/post_code.h>
-
-/*
- * This is the common entry point after DRAM has been initialized.
- */
- /*
- * eax: New stack address
- */
-
- /* Switch to the stack in RAM */
- movl %eax, %esp
-
-#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
-
- /* SOC specific NEM */
- #include <soc/car_teardown.S>
-
-#else
-.extern fih_car
-
- post_code(POST_FSP_TEMP_RAM_EXIT)
-
- /* Calculate TempRamExit entry into FSP */
- movl fih_car, %ebp
- mov 0x40(%ebp), %eax
- add 0x1c(%ebp), %eax
-
- /* Build the call frame */
- pushl $0
-
- /* Call TempRamExit */
- call *%eax
- add $4, %esp
- cmp $0, %eax
- jz 1f
- /*
- * Failures for post code BC - failed in TempRamExit
- *
- * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully.
- * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
- * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
- * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed.
- */
- movb $0xBC, %ah
- jmp .Lhlt
-1:
-#endif
- /* Display the MTRRs */
- call soc_display_mtrrs
-
- /*
- * The stack contents are initialized in src/soc/intel/common/stack.c
- * to be the following:
- *
- * *
- * *
- * *
- * +36: MTRR mask 1 63:32
- * +32: MTRR mask 1 31:0
- * +28: MTRR base 1 63:32
- * +24: MTRR base 1 31:0
- * +20: MTRR mask 0 63:32
- * +16: MTRR mask 0 31:0
- * +12: MTRR base 0 63:32
- * +8: MTRR base 0 31:0
- * +4: Number of MTRRs to setup (described above)
- * +0: Number of variable MTRRs to clear
- */
-
-#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
- push %esp
- call soc_set_mtrrs
-
- /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */
- movl %eax, %esp
-#else
- /* Clear all of the variable MTRRs. */
- popl %ebx
- movl $MTRR_PHYS_BASE(0), %ecx
- clr %eax
- clr %edx
-
-1:
- testl %ebx, %ebx
- jz 1f
- wrmsr /* Write MTRR base. */
- inc %ecx
- wrmsr /* Write MTRR mask. */
- inc %ecx
- dec %ebx
- jmp 1b
-
-1:
- /* Get number of MTRRs. */
- popl %ebx
- movl $MTRR_PHYS_BASE(0), %ecx
-2:
- testl %ebx, %ebx
- jz 2f
-
- /* Low 32 bits of MTRR base. */
- popl %eax
- /* Upper 32 bits of MTRR base. */
- popl %edx
- /* Write MTRR base. */
- wrmsr
- inc %ecx
- /* Low 32 bits of MTRR mask. */
- popl %eax
- /* Upper 32 bits of MTRR mask. */
- popl %edx
- /* Write MTRR mask. */
- wrmsr
- inc %ecx
-
- dec %ebx
- jmp 2b
-2:
-#endif /* CONFIG_SOC_SETS_MTRRS */
-
- post_code(0x39)
-
- /* And enable cache again after setting MTRRs. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x3a)
-
-#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
- call soc_enable_mtrrs
-#else
- /* Enable MTRR. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- orl $MTRR_DEF_TYPE_EN, %eax
- wrmsr
-#endif /* CONFIG_SOC_SETS_MTRRS */
-
- post_code(0x3b)
-
- /* Invalidate the cache again. */
- invd
-
- post_code(0x3c)
-
-__main:
- post_code(POST_PREPARE_RAMSTAGE)
- cld /* Clear direction flag. */
- call after_cache_as_ram
-
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
deleted file mode 100644
index 6e7e50b..0000000
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
- * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Replacement for cache_as_ram.inc when using the FSP binary. This code
- * locates the FSP binary, initializes the cache as RAM and performs the
- * first stage of initialization. Next this code switches the stack from
- * the cache to RAM and then disables the cache as RAM. Finally this code
- * performs the final stage of initialization.
- */
-
-#include <rules.h>
-
-#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
-
- /*
- * eax: BIST value
- * mm0: low 32-bits of TSC value
- * mm1: high 32-bits of TSC value
- */
- movl %eax, %edi
-cache_as_ram:
- post_code(0x20)
-
-#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
-
- /*
- * SOC specific setup
- * NOTE: This has to preserve the registers
- * mm0, mm1 and edi.
- */
- #include <soc/car_setup.S>
-
- post_code(0x28)
-
-#endif
-
- /*
- * Find the FSP binary in cbfs.
- * Make a fake stack that has the return value back to this code.
- */
- lea fake_fsp_stack, %esp
- jmp find_fsp
-find_fsp_ret:
- /* Save the FSP location */
- mov %eax, %ebp
-
- /*
- * Only when a valid FSP binary is found at CONFIG_FSP_LOC is
- * the returned FSP_INFO_HEADER structure address above the base
- * address of FSP binary specified by the CONFIG_FSP_LOC value.
- * All of the error values are in the 0x8xxxxxxx range which are
- * below the CONFIG_FSP_LOC value.
- */
- cmp $CONFIG_FSP_LOC, %eax
- jbe halt1
-
- post_code(POST_FSP_TEMP_RAM_INIT)
-
- /* Calculate entry into FSP */
- mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
- add 0x1c(%ebp), %eax /* add in the offset for FSP */
-
- /*
- * Pass early init variables on a fake stack (no memory yet)
- * as well as the return location
- */
- lea CAR_init_stack, %esp
-
- /*
- * BIST value is zero
- * eax: TempRamInitApi address
- * ebp: FSP_INFO_HEADER address
- * edi: BIST value
- * esi: Not used
- * mm0: low 32-bits of TSC value
- * mm1: high 32-bits of TSC value
- */
-
- /* call FSP binary to setup temporary stack */
- jmp *%eax
-
-CAR_init_done:
- addl $4, %esp
-
- /*
- * ebp: FSP_INFO_HEADER address
- * ecx: Temp RAM base
- * edx: Temp RAM top
- * edi: BIST value
- * mm0: low 32-bits of TSC value
- * mm1: high 32-bits of TSC value
- */
-
- cmp $0, %eax
- jne halt2
-
- /* Setup bootloader stack */
- movl %edx, %esp
-
- /*
- * ebp: FSP_INFO_HEADER address
- * ecx: Temp RAM base
- * edx: Temp RAM top
- * edi: BIST value
- * esp: Top of stack in temp RAM
- * mm0: low 32-bits of TSC value
- * mm1: high 32-bits of TSC value
- */
-
- /* Create cache_as_ram_params on stack */
- pushl %edx /* bootloader CAR end */
- pushl %ecx /* bootloader CAR begin */
- pushl %ebp /* FSP_INFO_HEADER */
- pushl %edi /* bist */
- movd %mm1, %eax
- pushl %eax /* tsc[63:32] */
- movd %mm0, %eax
- pushl %eax /* tsc[31:0] */
- pushl %esp /* pointer to cache_as_ram_params */
-
- /* Save FSP_INFO_HEADER location in ebx */
- mov %ebp, %ebx
-
- /* Coreboot assumes stack/heap region will be zero */
- cld
- movl %ecx, %edi
- neg %ecx
- /* Only clear up to current stack value. */
- add %esp, %ecx
- shrl $2, %ecx
- xorl %eax, %eax
- rep stosl
-
-before_romstage:
- post_code(0x2A)
-
- /* Call cache_as_ram_main(struct cache_as_ram_params *) */
- call cache_as_ram_main
-
-/* One will never return from cache_as_ram_main() in verstage so there's
- * no such thing as after ram init. */
-#if !ENV_VERSTAGE
-#include "after_raminit.S"
-#endif
-
- movb $0x69, %ah
- jmp .Lhlt
-
-halt1:
- /*
- * Failures for postcode 0xBA - failed in fsp_fih_early_find()
- *
- * Values are:
- * 0x01 - FV signature, "_FVH" not present
- * 0x02 - FFS GUID not present
- * 0x03 - FSP INFO Header not found
- * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
- * a different location, or does it need to be?
- * 0x05 - FSP INFO Header signature "FSPH" not found
- * 0x06 - FSP Image ID is not the expected ID.
- */
- movb $0xBA, %ah
- jmp .Lhlt
-
-halt2:
- /*
- * Failures for postcode 0xBB - failed in the FSP:
- *
- * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
- * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
- * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
- * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
- * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
- * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
- */
- movb $0xBB, %ah
- jmp .Lhlt
-
-.Lhlt:
- xchg %al, %ah
-#if IS_ENABLED(CONFIG_POST_IO)
- outb %al, $CONFIG_POST_IO_PORT
-#else
- post_code(POST_DEAD_CODE)
-#endif
- movl $LHLT_DELAY, %ecx
-.Lhlt_Delay:
- outb %al, $0xED
- loop .Lhlt_Delay
- jmp .Lhlt
-
-/*
- * esp is set to this location so that the call into and return from the FSP
- * in find_fsp will work.
- */
- .align 4
-fake_fsp_stack:
- .long find_fsp_ret
- .long CONFIG_FSP_LOC /* FSP base address */
-
-CAR_init_params:
- .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
- .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
- .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
- .long CONFIG_ROM_SIZE /* Total Firmware Length */
-
-CAR_init_stack:
- .long CAR_init_done
- .long CAR_init_params
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
deleted file mode 100644
index b525a62..0000000
--- a/src/drivers/intel/fsp1_1/car.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/early_variables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <fsp/car.h>
-#include <fsp/util.h>
-#include <program_loading.h>
-#include <soc/intel/common/util.h>
-#include <timestamp.h>
-
-FSP_INFO_HEADER *fih_car CAR_GLOBAL;
-
-/* Save FSP_INFO_HEADER for TempRamExit() call in assembly. */
-static inline void set_fih_car(FSP_INFO_HEADER *fih)
-{
- /* This variable is written in the raw form because it's only
- * ever accessed in code that that has the cache-as-ram enabled. The
- * assembly routine which tears down cache-as-ram utilizes this
- * variable for determining where to find FSP. */
- fih_car = fih;
-}
-
-asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
-{
- /* Initialize timestamp book keeping only once. */
- timestamp_init(car_params->tsc);
-
- /* Call into pre-console init code then initialize console. */
- car_soc_pre_console_init();
- car_mainboard_pre_console_init();
- console_init();
-
- printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
-
- printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
- printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
-
- if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE ||
- car_params->bootloader_car_end !=
- (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) {
- printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n",
- CONFIG_DCACHE_RAM_BASE,
- CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE,
- (long)car_params->bootloader_car_start,
- (long)car_params->bootloader_car_end);
- }
-
- car_soc_post_console_init();
- car_mainboard_post_console_init();
-
- /* Ensure the EC is in the right mode for recovery */
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) &&
- !IS_ENABLED(CONFIG_SEPARATE_VERSTAGE))
- google_chromeec_early_init();
-
- set_fih_car(car_params->fih);
-
- /* Return new stack value in ram back to assembly stub. */
- return cache_as_ram_stage_main(car_params->fih);
-}
-
-/* Entry point taken when romstage is called after a separate verstage. */
-asmlinkage void *romstage_after_verstage(void)
-{
- /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
- * is still enabled. We can directly access work buffer here. */
- FSP_INFO_HEADER *fih;
- struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
-
- console_init();
-
- if (prog_locate(&fsp)) {
- fih = NULL;
- printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp));
- } else
- /* This leaks a mapping which this code assumes is benign as
- * the flash is memory mapped CPU's address space. */
- fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp)));
-
- set_fih_car(fih);
-
- /* Return new stack value in ram back to assembly stub. */
- return cache_as_ram_stage_main(fih);
-}
-
-asmlinkage void after_cache_as_ram(void *chipset_context)
-{
- timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
- printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
- soc_display_mtrrs();
-
- after_cache_as_ram_stage();
-}
-
-void __attribute__((weak)) car_mainboard_pre_console_init(void)
-{
-}
-
-void __attribute__((weak)) car_soc_pre_console_init(void)
-{
-}
-
-void __attribute__((weak)) car_mainboard_post_console_init(void)
-{
-}
-
-void __attribute__((weak)) car_soc_post_console_init(void)
-{
-}
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c
deleted file mode 100644
index f531d76..0000000
--- a/src/drivers/intel/fsp1_1/fsp_gop.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boot/coreboot_tables.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <fsp/util.h>
-#include <lib.h>
-
-/* Reading VBT table from flash */
-const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len)
-{
- size_t vbt_size;
- union {
- const optionrom_vbt_t *data;
- uint32_t *signature;
- } vbt;
-
- /* Locate the vbt file in cbfs */
- vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_OPTIONROM,
- &vbt_size);
- if (!vbt.data) {
- printk(BIOS_INFO,
- "FSP_INFO: VBT data file (vbt.bin) not found in CBFS");
- return NULL;
- }
-
- /* Validate the vbt file */
- if (*vbt.signature != VBT_SIGNATURE) {
- printk(BIOS_WARNING,
- "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n");
- return NULL;
- }
- *vbt_len = vbt_size;
- printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n",
- vbt.data, *vbt_len);
-
-#if IS_ENABLED(CONFIG_DISPLAY_VBT)
- /* Display the vbt file contents */
- printk(BIOS_DEBUG, "VBT Data:\n");
- hexdump(vbt.data, *vbt_len);
- printk(BIOS_DEBUG, "\n");
-#endif
-
- /* Return the pointer to the vbt file data */
- return vbt.data;
-}
-
-void lb_framebuffer(struct lb_header *header)
-{
- struct lb_framebuffer *framebuffer;
- framebuffer = (struct lb_framebuffer *)lb_new_record(header);
-
- VOID *hob_list_ptr;
- hob_list_ptr = get_hob_list();
- const EFI_GUID vbt_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
- u32 *vbt_hob;
- EFI_PEI_GRAPHICS_INFO_HOB *vbt_gop;
- vbt_hob = get_next_guid_hob(&vbt_guid, hob_list_ptr);
- if (vbt_hob == NULL) {
- printk(BIOS_ERR, "FSP_ERR: Graphics Data HOB is not present\n");
- return;
- } else {
- printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n");
- vbt_gop = GET_GUID_HOB_DATA(vbt_hob);
- }
-
- framebuffer->physical_address = vbt_gop->FrameBufferBase;
- framebuffer->x_resolution = vbt_gop->GraphicsMode.HorizontalResolution;
- framebuffer->y_resolution = vbt_gop->GraphicsMode.VerticalResolution;
- framebuffer->bytes_per_line = vbt_gop->GraphicsMode.PixelsPerScanLine
- * 4;
- framebuffer->bits_per_pixel = 32;
- framebuffer->red_mask_pos = 16;
- framebuffer->red_mask_size = 8;
- framebuffer->green_mask_pos = 8;
- framebuffer->green_mask_size = 8;
- framebuffer->blue_mask_pos = 0;
- framebuffer->blue_mask_size = 8;
- framebuffer->reserved_mask_pos = 24;
- framebuffer->reserved_mask_size = 8;
- framebuffer->tag = LB_TAG_FRAMEBUFFER;
- framebuffer->size = sizeof(*framebuffer);
-}
diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c
deleted file mode 100644
index 89d7cd9..0000000
--- a/src/drivers/intel/fsp1_1/fsp_relocate.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cbmem.h>
-#include <commonlib/fsp1_1.h>
-#include <fsp/util.h>
-
-int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src)
-{
- void *new_loc;
- void *fih;
- ssize_t fih_offset;
- size_t size = region_device_sz(fsp_src);
-
- new_loc = cbmem_add(CBMEM_ID_REFCODE, size);
-
- if (new_loc == NULL) {
- printk(BIOS_ERR, "ERROR: Unable to load FSP into memory.\n");
- return -1;
- }
-
- if (rdev_readat(fsp_src, new_loc, 0, size) != size) {
- printk(BIOS_ERR, "ERROR: Can't read FSP's region device.\n");
- return -1;
- }
-
- fih_offset = fsp1_1_relocate((uintptr_t)new_loc, new_loc, size);
-
- if (fih_offset <= 0) {
- printk(BIOS_ERR, "ERROR: FSP relocation faiulre.\n");
- return -1;
- }
-
- fih = (void *)((uint8_t *)new_loc + fih_offset);
-
- prog_set_area(fsp_relocd, new_loc, size);
- prog_set_entry(fsp_relocd, fih, NULL);
-
- return 0;
-}
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
deleted file mode 100644
index 1aa3aec..0000000
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <bootstate.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <fsp/util.h>
-#include <timestamp.h>
-
-/* Locate the FSP binary in the coreboot filesystem */
-FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address)
-{
- union {
- EFI_FFS_FILE_HEADER *ffh;
- FSP_INFO_HEADER *fih;
- EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh;
- EFI_FIRMWARE_VOLUME_HEADER *fvh;
- EFI_RAW_SECTION *rs;
- u8 *u8;
- u32 u32;
- } fsp_ptr;
- static const union {
- char str_id[8];
- u32 int_id[2];
- } fsp_id = {
- .str_id = CONFIG_FSP_IMAGE_ID_STRING
- };
-
- u32 *image_id;
-
- for (;;) {
- /* Get the FSP binary base address in CBFS */
- fsp_ptr.u32 = fsp_base_address;
-
- /* Check the FV signature, _FVH */
- if (fsp_ptr.fvh->Signature != 0x4856465F) {
- fsp_ptr.u8 = (u8 *)ERROR_NO_FV_SIG;
- break;
- }
-
- /* Locate the file header which follows the FV header. */
- fsp_ptr.u8 += fsp_ptr.fvh->ExtHeaderOffset;
- fsp_ptr.u8 += fsp_ptr.fveh->ExtHeaderSize;
- fsp_ptr.u8 = (u8 *)ALIGN_UP(fsp_ptr.u32, 8);
-
- /* Check the FFS GUID */
- if ((((u32 *)&fsp_ptr.ffh->Name)[0] != 0x912740BE)
- || (((u32 *)&fsp_ptr.ffh->Name)[1] != 0x47342284)
- || (((u32 *)&fsp_ptr.ffh->Name)[2] != 0xB08471B9)
- || (((u32 *)&fsp_ptr.ffh->Name)[3] != 0x0C3F3527)) {
- fsp_ptr.u8 = (u8 *)ERROR_NO_FFS_GUID;
- break;
- }
-
- /* Locate the Raw Section Header */
- fsp_ptr.u8 += sizeof(EFI_FFS_FILE_HEADER);
-
- if (fsp_ptr.rs->Type != EFI_SECTION_RAW) {
- fsp_ptr.u8 = (u8 *)ERROR_NO_INFO_HEADER;
- break;
- }
-
- /* Locate the FSP INFO Header which follows the Raw Header. */
- fsp_ptr.u8 += sizeof(EFI_RAW_SECTION);
-
- /* Verify that the FSP base address.*/
- if (fsp_ptr.fih->ImageBase != fsp_base_address) {
- fsp_ptr.u8 = (u8 *)ERROR_IMAGEBASE_MISMATCH;
- break;
- }
-
- /* Verify the FSP Signature */
- if (fsp_ptr.fih->Signature != FSP_SIG) {
- fsp_ptr.u8 = (u8 *)ERROR_INFO_HEAD_SIG_MISMATCH;
- break;
- }
-
- /* Verify the FSP ID */
- image_id = (u32 *)&fsp_ptr.fih->ImageId[0];
- if ((image_id[0] != fsp_id.int_id[0])
- || (image_id[1] != fsp_id.int_id[1]))
- fsp_ptr.u8 = (u8 *)ERROR_FSP_SIG_MISMATCH;
- break;
- }
-
- return fsp_ptr.fih;
-}
-
-void print_fsp_info(FSP_INFO_HEADER *fsp_header)
-{
- u8 *fsp_base;
-
- fsp_base = (u8 *)fsp_header->ImageBase;
- printk(BIOS_SPEW, "FSP_INFO_HEADER: %p\n", fsp_header);
- printk(BIOS_INFO, "FSP Signature: %c%c%c%c%c%c%c%c\n",
- fsp_header->ImageId[0], fsp_header->ImageId[1],
- fsp_header->ImageId[2], fsp_header->ImageId[3],
- fsp_header->ImageId[4], fsp_header->ImageId[5],
- fsp_header->ImageId[6], fsp_header->ImageId[7]);
- printk(BIOS_INFO, "FSP Header Version: %d\n",
- fsp_header->HeaderRevision);
- printk(BIOS_INFO, "FSP Revision: %d.%d.%d.%d\n",
- (u8)((fsp_header->ImageRevision >> 24) & 0xff),
- (u8)((fsp_header->ImageRevision >> 16) & 0xff),
- (u8)((fsp_header->ImageRevision >> 8) & 0xff),
- (u8)(fsp_header->ImageRevision & 0xff));
-#if IS_ENABLED(CONFIG_DISPLAY_FSP_ENTRY_POINTS)
- printk(BIOS_SPEW, "FSP Entry Points:\n");
- printk(BIOS_SPEW, " 0x%p: Image Base\n", fsp_base);
- printk(BIOS_SPEW, " 0x%p: TempRamInit\n",
- &fsp_base[fsp_header->TempRamInitEntryOffset]);
- printk(BIOS_SPEW, " 0x%p: FspInit\n",
- &fsp_base[fsp_header->FspInitEntryOffset]);
- if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) {
- printk(BIOS_SPEW, " 0x%p: MemoryInit\n",
- &fsp_base[fsp_header->FspMemoryInitEntryOffset]);
- printk(BIOS_SPEW, " 0x%p: TempRamExit\n",
- &fsp_base[fsp_header->TempRamExitEntryOffset]);
- printk(BIOS_SPEW, " 0x%p: SiliconInit\n",
- &fsp_base[fsp_header->FspSiliconInitEntryOffset]);
- }
- printk(BIOS_SPEW, " 0x%p: NotifyPhase\n",
- &fsp_base[fsp_header->NotifyPhaseEntryOffset]);
- printk(BIOS_SPEW, " 0x%p: Image End\n",
- &fsp_base[fsp_header->ImageSize]);
-#endif
-}
-
-void fsp_notify(u32 phase)
-{
- FSP_NOTIFY_PHASE notify_phase_proc;
- NOTIFY_PHASE_PARAMS notify_phase_params;
- EFI_STATUS status;
- FSP_INFO_HEADER *fsp_header_ptr;
-
- fsp_header_ptr = fsp_get_fih();
- if (fsp_header_ptr == NULL) {
- fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC);
- if ((u32)fsp_header_ptr < 0xff) {
- /* output something in case there is no serial */
- post_code(0x4F);
- die("Can't find the FSP!\n");
- }
- }
-
- /* call FSP PEI to Notify PostPciEnumeration */
- notify_phase_proc = (FSP_NOTIFY_PHASE)(fsp_header_ptr->ImageBase +
- fsp_header_ptr->NotifyPhaseEntryOffset);
- notify_phase_params.Phase = phase;
-
- if (phase == EnumInitPhaseReadyToBoot) {
- timestamp_add_now(TS_FSP_BEFORE_FINALIZE);
- post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
- } else {
- timestamp_add_now(TS_FSP_BEFORE_ENUMERATE);
- post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
- }
-
- status = notify_phase_proc(¬ify_phase_params);
-
- timestamp_add_now(phase == EnumInitPhaseReadyToBoot ?
- TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE);
-
- if (status != 0)
- printk(BIOS_ERR, "FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n",
- phase, status);
-}
-
-static void fsp_notify_boot_state_callback(void *arg)
-{
- u32 phase = (u32)arg;
-
- printk(BIOS_SPEW, "Calling FspNotify(0x%08x)\n", phase);
- fsp_notify(phase);
-}
-
-BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT,
- fsp_notify_boot_state_callback,
- (void *)EnumInitPhaseAfterPciEnumeration);
-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT,
- fsp_notify_boot_state_callback,
- (void *)EnumInitPhaseReadyToBoot);
-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
- fsp_notify_boot_state_callback,
- (void *)EnumInitPhaseReadyToBoot);
-
-struct fsp_runtime {
- uint32_t fih;
- uint32_t hob_list;
-} __attribute__((packed));
-
-
-void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list)
-{
- struct fsp_runtime *fspr;
-
- fspr = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*fspr));
-
- if (fspr == NULL)
- die("Can't save FSP runtime information.\n");
-
- fspr->fih = (uintptr_t)fih;
- fspr->hob_list = (uintptr_t)hob_list;
-}
-
-FSP_INFO_HEADER *fsp_get_fih(void)
-{
- struct fsp_runtime *fspr;
-
- fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME);
-
- if (fspr == NULL)
- return NULL;
-
- return (void *)(uintptr_t)fspr->fih;
-}
-
-void *fsp_get_hob_list(void)
-{
- struct fsp_runtime *fspr;
-
- fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME);
-
- if (fspr == NULL)
- return NULL;
-
- return (void *)(uintptr_t)fspr->hob_list;
-}
-
-void fsp_update_fih(FSP_INFO_HEADER *fih)
-{
- struct fsp_runtime *fspr;
-
- fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME);
-
- if (fspr == NULL)
- die("Can't update FSP runtime information.\n");
-
- fspr->fih = (uintptr_t)fih;
-}
-
-void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old,
- uint64_t new)
-{
- if (old == new) {
- switch (size) {
- case 1:
- printk(BIOS_SPEW, " 0x%02llx: %s\n", new, name);
- break;
-
- case 2:
- printk(BIOS_SPEW, " 0x%04llx: %s\n", new, name);
- break;
-
- case 4:
- printk(BIOS_SPEW, " 0x%08llx: %s\n", new, name);
- break;
-
- case 8:
- printk(BIOS_SPEW, " 0x%016llx: %s\n", new, name);
- break;
- }
- } else {
- switch (size) {
- case 1:
- printk(BIOS_SPEW, " 0x%02llx --> 0x%02llx: %s\n", old,
- new, name);
- break;
-
- case 2:
- printk(BIOS_SPEW, " 0x%04llx --> 0x%04llx: %s\n", old,
- new, name);
- break;
-
- case 4:
- printk(BIOS_SPEW, " 0x%08llx --> 0x%08llx: %s\n", old,
- new, name);
- break;
-
- case 8:
- printk(BIOS_SPEW, " 0x%016llx --> 0x%016llx: %s\n",
- old, new, name);
- break;
- }
- }
-}
diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c
deleted file mode 100644
index c0816e9..0000000
--- a/src/drivers/intel/fsp1_1/hob.c
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/early_variables.h>
-#include <arch/hlt.h>
-#include <bootstate.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <fsp/util.h>
-#include <ip_checksum.h>
-#include <lib.h> // hexdump
-#include <string.h>
-
-/* Compares two EFI GUIDs. Returns true of the GUIDs match, false otherwise. */
-static bool compare_guid(const EFI_GUID *guid1, const EFI_GUID *guid2)
-{
- return !memcmp(guid1, guid2, sizeof(EFI_GUID));
-}
-
-/* Returns the pointer to the HOB list. */
-void *get_hob_list(void)
-{
- void *hob_list;
-
- hob_list = fsp_get_hob_list();
- if (hob_list == NULL)
- die("Call fsp_set_runtime() before this call!\n");
- return hob_list;
-}
-
-/* Returns the next instance of a HOB type from the starting HOB. */
-void *get_next_hob(uint16_t type, const void *hob_start)
-{
- EFI_PEI_HOB_POINTERS hob;
-
- if (!hob_start)
- return NULL;
-
- hob.Raw = (UINT8 *)hob_start;
-
- /* Parse the HOB list until end of list or matching type is found. */
- while (!END_OF_HOB_LIST(hob.Raw)) {
- if (hob.Header->HobType == type)
- return hob.Raw;
- if (GET_HOB_LENGTH(hob.Raw) < sizeof(*hob.Header))
- break;
- hob.Raw = GET_NEXT_HOB(hob.Raw);
- }
- return NULL;
-}
-
-/* Returns the first instance of a HOB type among the whole HOB list. */
-void *get_first_hob(uint16_t type)
-{
- return get_next_hob(type, get_hob_list());
-}
-
-/* Returns the next instance of the matched GUID HOB from the starting HOB. */
-void *get_next_guid_hob(const EFI_GUID * guid, const void *hob_start)
-{
- EFI_PEI_HOB_POINTERS hob;
-
- hob.Raw = (uint8_t *)hob_start;
- while ((hob.Raw = get_next_hob(EFI_HOB_TYPE_GUID_EXTENSION, hob.Raw))
- != NULL) {
- if (compare_guid(guid, &hob.Guid->Name))
- break;
- hob.Raw = GET_NEXT_HOB(hob.Raw);
- }
- return hob.Raw;
-}
-
-/*
- * Returns the first instance of the matched GUID HOB among the whole HOB list.
- */
-void *get_first_guid_hob(const EFI_GUID *guid)
-{
- return get_next_guid_hob(guid, get_hob_list());
-}
-
-/*
- * Returns the next instance of the matching resource HOB from the starting HOB.
- */
-void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start)
-{
- EFI_PEI_HOB_POINTERS hob;
-
- hob.Raw = (UINT8 *)hob_start;
- while ((hob.Raw = get_next_hob(EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,
- hob.Raw)) != NULL) {
- if (compare_guid(guid, &hob.ResourceDescriptor->Owner))
- break;
- hob.Raw = GET_NEXT_HOB(hob.Raw);
- }
- return hob.Raw;
-}
-
-/*
- * Returns the first instance of the matching resource HOB among the whole HOB
- * list.
- */
-void *get_first_resource_hob(const EFI_GUID *guid)
-{
- return get_next_resource_hob(guid, get_hob_list());
-}
-
-static void print_hob_mem_attributes(void *hob_ptr)
-{
- EFI_MEMORY_TYPE hob_mem_type;
- EFI_HOB_MEMORY_ALLOCATION *hob_memory_ptr = hob_ptr;
- u64 hob_mem_addr = hob_memory_ptr->AllocDescriptor.MemoryBaseAddress;
- u64 hob_mem_length = hob_memory_ptr->AllocDescriptor.MemoryLength;
-
- hob_mem_type = hob_memory_ptr->AllocDescriptor.MemoryType;
-
- static const char *hob_mem_type_names[15] = {
- [EfiReservedMemoryType] = "EfiReservedMemoryType",
- [EfiLoaderCode] = "EfiLoaderCode",
- [EfiLoaderData] = "EfiLoaderData",
- [EfiBootServicesCode] = "EfiBootServicesCode",
- [EfiBootServicesData] = "EfiBootServicesData",
- [EfiRuntimeServicesCode] = "EfiRuntimeServicesCode",
- [EfiRuntimeServicesData] = "EfiRuntimeServicesData",
- [EfiConventionalMemory] = "EfiConventionalMemory",
- [EfiUnusableMemory] = "EfiUnusableMemory",
- [EfiACPIReclaimMemory] = "EfiACPIReclaimMemory",
- [EfiACPIMemoryNVS] = "EfiACPIMemoryNVS",
- [EfiMemoryMappedIO] = "EfiMemoryMappedIO",
- [EfiMemoryMappedIOPortSpace] = "EfiMemoryMappedIOPortSpace",
- [EfiPalCode] = "EfiPalCode",
- [EfiMaxMemoryType] = "EfiMaxMemoryType",
- };
-
- if (hob_mem_type >= ARRAY_SIZE(hob_mem_type_names))
- hob_mem_type = EfiReservedMemoryType;
-
- printk(BIOS_SPEW, " Memory type %s (0x%x)\n",
- hob_mem_type_names[hob_mem_type],
- (u32)hob_mem_type);
- printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n",
- (unsigned long)hob_mem_addr,
- (unsigned long)hob_mem_length);
-}
-
-static void print_hob_resource_attributes(void *hob_ptr)
-{
- EFI_HOB_RESOURCE_DESCRIPTOR *hob_resource_ptr =
- (EFI_HOB_RESOURCE_DESCRIPTOR *)hob_ptr;
- u32 hob_res_type = hob_resource_ptr->ResourceType;
- u32 hob_res_attr = hob_resource_ptr->ResourceAttribute;
- u64 hob_res_addr = hob_resource_ptr->PhysicalStart;
- u64 hob_res_length = hob_resource_ptr->ResourceLength;
- const char *hob_res_type_str = NULL;
-
- /* HOB Resource Types */
- switch (hob_res_type) {
- case EFI_RESOURCE_SYSTEM_MEMORY:
- hob_res_type_str = "EFI_RESOURCE_SYSTEM_MEMORY";
- break;
- case EFI_RESOURCE_MEMORY_MAPPED_IO:
- hob_res_type_str = "EFI_RESOURCE_MEMORY_MAPPED_IO";
- break;
- case EFI_RESOURCE_IO:
- hob_res_type_str = "EFI_RESOURCE_IO";
- break;
- case EFI_RESOURCE_FIRMWARE_DEVICE:
- hob_res_type_str = "EFI_RESOURCE_FIRMWARE_DEVICE";
- break;
- case EFI_RESOURCE_MEMORY_MAPPED_IO_PORT:
- hob_res_type_str = "EFI_RESOURCE_MEMORY_MAPPED_IO_PORT";
- break;
- case EFI_RESOURCE_MEMORY_RESERVED:
- hob_res_type_str = "EFI_RESOURCE_MEMORY_RESERVED";
- break;
- case EFI_RESOURCE_IO_RESERVED:
- hob_res_type_str = "EFI_RESOURCE_IO_RESERVED";
- break;
- case EFI_RESOURCE_MAX_MEMORY_TYPE:
- hob_res_type_str = "EFI_RESOURCE_MAX_MEMORY_TYPE";
- break;
- default:
- hob_res_type_str = "EFI_RESOURCE_UNKNOWN";
- break;
- }
-
- printk(BIOS_SPEW, " Resource %s (0x%0x) has attributes 0x%0x\n",
- hob_res_type_str, hob_res_type, hob_res_attr);
- printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n",
- (unsigned long)hob_res_addr,
- (unsigned long)hob_res_length);
-}
-
-static const char *get_hob_type_string(void *hob_ptr)
-{
- EFI_PEI_HOB_POINTERS hob;
- const char *hob_type_string;
- const EFI_GUID fsp_reserved_guid =
- FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID;
- const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
- const EFI_GUID bootldr_tmp_mem_guid =
- FSP_BOOTLOADER_TEMP_MEMORY_HOB_GUID;
- const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
- const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
- const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
-
- hob.Header = (EFI_HOB_GENERIC_HEADER *)hob_ptr;
- switch (hob.Header->HobType) {
- case EFI_HOB_TYPE_HANDOFF:
- hob_type_string = "EFI_HOB_TYPE_HANDOFF";
- break;
- case EFI_HOB_TYPE_MEMORY_ALLOCATION:
- hob_type_string = "EFI_HOB_TYPE_MEMORY_ALLOCATION";
- break;
- case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
- if (compare_guid(&fsp_reserved_guid, &hob.Guid->Name))
- hob_type_string = "FSP_RESERVED_MEMORY_RESOURCE_HOB";
- else if (compare_guid(&bootldr_tolum_guid, &hob.Guid->Name))
- hob_type_string = "FSP_BOOTLOADER_TOLUM_HOB_GUID";
- else
- hob_type_string = "EFI_HOB_TYPE_RESOURCE_DESCRIPTOR";
- break;
- case EFI_HOB_TYPE_GUID_EXTENSION:
- if (compare_guid(&bootldr_tmp_mem_guid, &hob.Guid->Name))
- hob_type_string = "FSP_BOOTLOADER_TEMP_MEMORY_HOB";
- else if (compare_guid(&mrc_guid, &hob.Guid->Name))
- hob_type_string = "FSP_NON_VOLATILE_STORAGE_HOB";
- else if (compare_guid(&graphics_info_guid, &hob.Guid->Name))
- hob_type_string = "EFI_PEI_GRAPHICS_INFO_HOB_GUID";
- else if (compare_guid(&memory_info_hob_guid, &hob.Guid->Name))
- hob_type_string = "FSP_SMBIOS_MEMORY_INFO_GUID";
- else
- hob_type_string = "EFI_HOB_TYPE_GUID_EXTENSION";
- break;
- case EFI_HOB_TYPE_MEMORY_POOL:
- hob_type_string = "EFI_HOB_TYPE_MEMORY_POOL";
- break;
- case EFI_HOB_TYPE_UNUSED:
- hob_type_string = "EFI_HOB_TYPE_UNUSED";
- break;
- case EFI_HOB_TYPE_END_OF_HOB_LIST:
- hob_type_string = "EFI_HOB_TYPE_END_OF_HOB_LIST";
- break;
- default:
- hob_type_string = "EFI_HOB_TYPE_UNRECOGNIZED";
- break;
- }
-
- return hob_type_string;
-}
-
-/*
- * Print out a structure of all the HOBs
- * that match a certain type:
- * Print all types (0x0000)
- * EFI_HOB_TYPE_HANDOFF (0x0001)
- * EFI_HOB_TYPE_MEMORY_ALLOCATION (0x0002)
- * EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (0x0003)
- * EFI_HOB_TYPE_GUID_EXTENSION (0x0004)
- * EFI_HOB_TYPE_MEMORY_POOL (0x0007)
- * EFI_HOB_TYPE_UNUSED (0xFFFE)
- * EFI_HOB_TYPE_END_OF_HOB_LIST (0xFFFF)
- */
-void print_hob_type_structure(u16 hob_type, void *hob_list_ptr)
-{
- u32 *current_hob;
- u32 *next_hob = 0;
- u8 last_hob = 0;
- u32 current_type;
- const char *current_type_str;
-
- current_hob = hob_list_ptr;
-
- /*
- * Print out HOBs of our desired type until
- * the end of the HOB list
- */
- printk(BIOS_DEBUG, "\n=== FSP HOB Data Structure ===\n");
- printk(BIOS_DEBUG, "0x%p: hob_list_ptr\n", hob_list_ptr);
- do {
- EFI_HOB_GENERIC_HEADER *current_header_ptr =
- (EFI_HOB_GENERIC_HEADER *)current_hob;
-
- /* Get the type of this HOB */
- current_type = current_header_ptr->HobType;
- current_type_str = get_hob_type_string(current_hob);
-
- if (current_type == hob_type || hob_type == 0x0000) {
- printk(BIOS_DEBUG, "HOB %p is an %s (type 0x%0x)\n",
- current_hob, current_type_str,
- current_type);
- switch (current_type) {
- case EFI_HOB_TYPE_MEMORY_ALLOCATION:
- print_hob_mem_attributes(current_hob);
- break;
- case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
- print_hob_resource_attributes(current_hob);
- break;
- }
- }
-
- /* Check for end of HOB list */
- last_hob = END_OF_HOB_LIST(current_hob);
- if (!last_hob) {
- /* Get next HOB pointer */
- next_hob = GET_NEXT_HOB(current_hob);
-
- /* Start on next HOB */
- current_hob = next_hob;
- }
- } while (!last_hob);
- printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n");
-}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/api.h b/src/drivers/intel/fsp1_1/include/fsp/api.h
deleted file mode 100644
index 773b3c3..0000000
--- a/src/drivers/intel/fsp1_1/include/fsp/api.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _FSP1_1_API_H_
-#define _FSP1_1_API_H_
-
-/* All the FSP headers need to have UEFI types provided before inclusion. */
-#include <fsp/uefi_binding.h>
-
-/*
- * Intel's code does not have a handle on changing global packing state.
- * Therefore, one needs to protect against packing policies that are set
- * globally for a compliation unit just by including a header file.
- */
-#pragma pack(push)
-
-#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h>
-#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h>
-
-/* Restore original packing policy. */
-#pragma pack(pop)
-
-#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h
deleted file mode 100644
index 56400a7..0000000
--- a/src/drivers/intel/fsp1_1/include/fsp/car.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef FSP1_1_CAR_H
-#define FSP1_1_CAR_H
-
-#include <arch/cpu.h>
-#include <fsp/api.h>
-#include <stdint.h>
-
-/* cache-as-ram support for FSP 1.1. */
-struct cache_as_ram_params {
- uint64_t tsc;
- uint32_t bist;
- FSP_INFO_HEADER *fih;
- uintptr_t bootloader_car_start;
- uintptr_t bootloader_car_end;
-};
-
-/* Entry points from the cache-as-ram assembly code. */
-asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
-asmlinkage void after_cache_as_ram(void *chipset_context);
-asmlinkage void *romstage_after_verstage(void);
-/* Per stage calls from the above two functions. The void * return from
- * cache_as_ram_stage_main() is the stack pointer to use in ram after
- * exiting cache-as-ram mode. */
-void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih);
-void after_cache_as_ram_stage(void);
-
-/* Mainboard and SoC initialization prior to console. */
-void car_mainboard_pre_console_init(void);
-void car_soc_pre_console_init(void);
-/* Mainboard and SoC initialization post console initialization. */
-void car_mainboard_post_console_init(void);
-void car_soc_post_console_init(void);
-
-#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/gma.h b/src/drivers/intel/fsp1_1/include/fsp/gma.h
deleted file mode 100644
index 8797932..0000000
--- a/src/drivers/intel/fsp1_1/include/fsp/gma.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Chromium OS Authors
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _GMA_H_
-#define _GMA_H_
-
-#include <types.h>
-
-/* IGD PCI Configuration register */
-#define ASLS 0xfc /* OpRegion Base */
-#define SWSCI 0xe8 /* SWSCI Register */
-#define GSSCIE (1 << 0) /* SCI Event trigger */
-#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */
-
-/* mailbox 0: header */
-typedef struct {
- u8 signature[16];
- u32 size;
- u32 version;
- u8 sbios_version[32];
- u8 vbios_version[16];
- u8 driver_version[16];
- u32 mailboxes;
- u8 reserved[164];
-} __attribute__((packed)) opregion_header_t;
-
-#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
-#define IGD_OPREGION_VERSION 2
-
-#define IGD_MBOX1 (1 << 0)
-#define IGD_MBOX2 (1 << 1)
-#define IGD_MBOX3 (1 << 2)
-#define IGD_MBOX4 (1 << 3)
-#define IGD_MBOX5 (1 << 4)
-
-#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
- IGD_MBOX4 | IGD_MBOX5)
-#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
-
-#define SBIOS_VERSION_SIZE 32
-
-/* mailbox 1: public acpi methods */
-typedef struct {
- u32 drdy;
- u32 csts;
- u32 cevt;
- u8 reserved1[20];
- u32 didl[8];
- u32 cpdl[8];
- u32 cadl[8];
- u32 nadl[8];
- u32 aslp;
- u32 tidx;
- u32 chpd;
- u32 clid;
- u32 cdck;
- u32 sxsw;
- u32 evts;
- u32 cnot;
- u32 nrdy;
- u8 reserved2[60];
-} __attribute__((packed)) opregion_mailbox1_t;
-
-/* mailbox 2: software sci interface */
-typedef struct {
- u32 scic;
- u32 parm;
- u32 dslp;
- u8 reserved[244];
-} __attribute__((packed)) opregion_mailbox2_t;
-
-/* mailbox 3: power conservation */
-typedef struct {
- u32 ardy;
- u32 aslc;
- u32 tche;
- u32 alsi;
- u32 bclp;
- u32 pfit;
- u32 cblv;
- u16 bclm[20];
- u32 cpfm;
- u32 epfm;
- u8 plut[74];
- u32 pfmb;
- u32 ccdv;
- u32 pcft;
- u8 reserved[94];
-} __attribute__((packed)) opregion_mailbox3_t;
-
-#define IGD_BACKLIGHT_BRIGHTNESS 0xff
-#define IGD_INITIAL_BRIGHTNESS 0x64
-
-#define IGD_FIELD_VALID (1 << 31)
-#define IGD_WORD_FIELD_VALID (1 << 15)
-#define IGD_PFIT_STRETCH 6
-
-/* mailbox 4: vbt */
-typedef struct {
- u8 gvd1[7168];
-} __attribute__((packed)) opregion_vbt_t;
-
-/* IGD OpRegion */
-typedef struct {
- opregion_header_t header;
- opregion_mailbox1_t mailbox1;
- opregion_mailbox2_t mailbox2;
- opregion_mailbox3_t mailbox3;
- opregion_vbt_t vbt;
-} __attribute__((packed)) igd_opregion_t;
-
-/* Intel Video BIOS (Option ROM) */
-typedef struct {
- u16 signature;
- u8 size;
- u8 reserved[21];
- u16 pcir_offset;
- u16 vbt_offset;
-} __attribute__((packed)) optionrom_header_t;
-
-#define OPROM_SIGNATURE 0xaa55
-
-typedef struct {
- u32 signature;
- u16 vendor;
- u16 device;
- u16 reserved1;
- u16 length;
- u8 revision;
- u8 classcode[3];
- u16 imagelength;
- u16 coderevision;
- u8 codetype;
- u8 indicator;
- u16 reserved2;
-} __attribute__((packed)) optionrom_pcir_t;
-
-typedef struct {
- u8 hdr_signature[20];
- u16 hdr_version;
- u16 hdr_size;
- u16 hdr_vbt_size;
- u8 hdr_vbt_checksum;
- u8 hdr_reserved;
- u32 hdr_vbt_datablock;
- u32 hdr_aim[4];
- u8 datahdr_signature[16];
- u16 datahdr_version;
- u16 datahdr_size;
- u16 datahdr_datablocksize;
- u8 coreblock_id;
- u16 coreblock_size;
- u16 coreblock_biossize;
- u8 coreblock_biostype;
- u8 coreblock_releasestatus;
- u8 coreblock_hwsupported;
- u8 coreblock_integratedhw;
- u8 coreblock_biosbuild[4];
- u8 coreblock_biossignon[155];
-} __attribute__((packed)) optionrom_vbt_t;
-
-#define VBT_SIGNATURE 0x54425624
-
-#endif /* _GMA_H_ */
-
diff --git a/src/drivers/intel/fsp1_1/include/fsp/gop.h b/src/drivers/intel/fsp1_1/include/fsp/gop.h
deleted file mode 100644
index 66c8a3c..0000000
--- a/src/drivers/intel/fsp1_1/include/fsp/gop.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _FSP1_1_GOP_H_
-#define _FSP1_1_GOP_H_
-
-#include <fsp/gma.h>
-
-const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
-
-#endif /* _FSP1_1_GOP_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h
deleted file mode 100644
index 965bce6..0000000
--- a/src/drivers/intel/fsp1_1/include/fsp/memmap.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _COMMON_MEMMAP_H_
-#define _COMMON_MEMMAP_H_
-
-#include <types.h>
-
-/*
- * mmap_region_granularity must to return a size which is a positive non-zero
- * integer multiple of the SMM size when SMM is in use. When not using SMM,
- * this value should be set to 8 MiB.
- */
-size_t mmap_region_granularity(void);
-
-/* Fills in the arguments for the entire SMM region covered by chipset
- * protections. e.g. TSEG. */
-void smm_region(void **start, size_t *size);
-
-enum {
- /* SMM handler area. */
- SMM_SUBREGION_HANDLER,
- /* SMM cache region. */
- SMM_SUBREGION_CACHE,
- /* Chipset specific area. */
- SMM_SUBREGION_CHIPSET,
- /* Total sub regions supported. */
- SMM_SUBREGION_NUM,
-};
-
-/* Fills in the start and size for the requested SMM subregion. Returns
- * 0 on susccess, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
-
-#endif /* _COMMON_MEMMAP_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
deleted file mode 100644
index 5ce6aa8..0000000
--- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _INTEL_COMMON_RAMSTAGE_H_
-#define _INTEL_COMMON_RAMSTAGE_H_
-
-#include <fsp/util.h>
-#include <soc/intel/common/util.h>
-#include <stdint.h>
-
-/* Perform Intel silicon init. */
-void intel_silicon_init(void);
-void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup);
-/* Called after the silicon init code has run. */
-void soc_after_silicon_init(void);
-/* Initialize UPD data before SiliconInit call. */
-void soc_silicon_init_params(SILICON_INIT_UPD *params);
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params);
-void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
- SILICON_INIT_UPD *new);
-void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params);
-
-#endif /* _INTEL_COMMON_RAMSTAGE_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
deleted file mode 100644
index d07dc37..0000000
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _COMMON_ROMSTAGE_H_
-#define _COMMON_ROMSTAGE_H_
-
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <memory_info.h>
-#include <fsp/car.h>
-#include <fsp/util.h>
-#include <soc/intel/common/util.h>
-#include <soc/pei_wrapper.h>
-#include <soc/pm.h> /* chip_power_state */
-
-struct romstage_params {
- uint32_t fsp_version;
- struct chipset_power_state *power_state;
- struct pei_data *pei_data;
- void *chipset_context;
-};
-
-/*
- * FSP Boot Flow:
- * 1. src/cpu/x86/16bit/reset.inc
- * 2. src/cpu/x86/16bit/entry.inc
- * 3. other modules
- * 4. src/drivers/intel/fsp1_1/cache_as_ram.inc
- * 5. src/drivers/intel/fsp1_1/fsp_util.c/find_fsp
- * 6. FSP binary/TempRamInit
- * 7. src/drivers/intel/fsp1_1/cache_as_ram.inc - return
- * 8. src/soc/intel/common/romstage.c/romstage_main
- * 9 src/soc/.../romstage/.../soc_pre_console_init
- * 10 src/console/console.c/console_init
- * 11 src/soc/.../romstage/.../soc_romstage_init
- * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry
- * 13. src/soc/intel/common/romstage.c/romstage_common
- * 14 src/soc/.../romstage/.../soc_pre_raminit
- * 15. FSP binary/MemoryInit
- * 16. src/soc/intel/common/romstage.c/romstage_common - return
- * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return
- * 18. src/soc/intel/common/romstage.c/romstage_main - return
- * 19. src/soc/intel/common/stack.c/setup_stack_and_mttrs
- * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup
- * after call to romstage_main
- * 21. FSP binary/TempRamExit
- * 22. src/soc/intel/common/romstage.c/romstage_after_car
- * 23. FSP binary/SiliconInit
- * 24. src/soc/intel/common/romstage.c/romstage_after_car - return
- * 25. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
- * 26. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
- * 27. FSP binary/FspNotify
- * 28. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
- * 29. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
- * 30. FSP binary/FspNotify
- */
-
-void mainboard_check_ec_image(struct romstage_params *params);
-void mainboard_memory_init_params(struct romstage_params *params,
- MEMORY_INIT_UPD *memory_params);
-void mainboard_romstage_entry(struct romstage_params *params);
-void mainboard_save_dimm_info(struct romstage_params *params);
-void mainboard_add_dimm_info(struct romstage_params *params,
- struct memory_info *mem_info,
- int channel, int dimm, int index);
-void raminit(struct romstage_params *params);
-void report_memory_config(void);
-void romstage_common(struct romstage_params *params);
-asmlinkage void *romstage_main(FSP_INFO_HEADER *fih);
-void *setup_stack_and_mtrrs(void);
-void soc_after_ram_init(struct romstage_params *params);
-void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
- MEMORY_INIT_UPD *new);
-void soc_memory_init_params(struct romstage_params *params,
- MEMORY_INIT_UPD *upd);
-void soc_pre_ram_init(struct romstage_params *params);
-
-/*
- * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs.
- * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data.
- */
-asmlinkage void *soc_set_mtrrs(void *top_of_stack);
-asmlinkage void soc_enable_mtrrs(void);
-
-#endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h
deleted file mode 100644
index affb43f..0000000
--- a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _FSP1_1_SOC_BINDING_H_
-#define _FSP1_1_SOC_BINDING_H_
-
-/* All the FSP headers need to have UEFI types provided before inclusion. */
-#include <fsp/uefi_binding.h>
-
-/*
- * Intel's code does not have a handle on changing global packing state.
- * Therefore, one needs to protect against packing policies that are set
- * globally for a compliation unit just by including a header file.
- */
-#pragma pack(push)
-
-/*
- * This file is found in the soc / chipset directory. It is
- * a per implementation specific header. i.e. different FSP implementations
- * for different chipsets.
- */
-#include <FspUpdVpd.h>
-
-/* Restore original packing policy. */
-#pragma pack(pop)
-
-#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/stack.h b/src/drivers/intel/fsp1_1/include/fsp/stack.h
deleted file mode 100644
index e60360d..0000000
--- a/src/drivers/intel/fsp1_1/include/fsp/stack.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _COMMON_STACK_H_
-#define _COMMON_STACK_H_
-
-#include <stdint.h>
-
-static inline void *stack_push32(void *stack, uint32_t value)
-{
- uint32_t *stack32 = stack;
-
- stack32 = &stack32[-1];
- *stack32 = value;
- return stack32;
-}
-
-#endif /* _COMMON_STACK_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h
deleted file mode 100644
index ad5bd36..0000000
--- a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _FSP1_1_UEFI_BINDING_H_
-#define _FSP1_1_UEFI_BINDING_H_
-
-/*
- * Intel's code does not have a handle on changing global packing state.
- * Therefore, one needs to protect against packing policies that are set
- * globally for a compliation unit just by including a header file.
- */
-#pragma pack(push)
-
-/*
- * Pull in the UEFI types from 2.4. Smarter decisions can be made on what
- * version to bind to, but for now 2.4 is standard for FSP 1.1.
- */
-#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h>
-
-/* Restore original packing policy. */
-#pragma pack(pop)
-
-#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
deleted file mode 100644
index 07cf0c7..0000000
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef FSP1_1_UTIL_H
-#define FSP1_1_UTIL_H
-
-#include <rules.h>
-#include <fsp/api.h>
-/* Current users expect to get the SoC's FSP definitions by including util.h. */
-#include <fsp/soc_binding.h>
-#include <fsp/gop.h>
-#include <program_loading.h>
-#include <commonlib/region.h>
-
-/* find_fsp() should only be called from assembly code. */
-FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
-/* Set FSP's runtime information. */
-void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list);
-/* Use a new FSP_INFO_HEADER at runtime. */
-void fsp_update_fih(FSP_INFO_HEADER *fih);
-/* fsp_get_fih() is only valid after calling fsp_set_runtime(). */
-FSP_INFO_HEADER *fsp_get_fih(void);
-/* fsp_get_hob_list() is only valid after calling fsp_set_runtime(). */
-void *fsp_get_hob_list(void);
-void fsp_early_init(FSP_INFO_HEADER *fsp_info);
-void fsp_notify(u32 phase);
-void print_hob_type_structure(u16 hob_type, void *hob_list_ptr);
-void print_fsp_info(FSP_INFO_HEADER *fsp_header);
-void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid,
- const void *hob_start);
-void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
-void *get_first_resource_hob(const EFI_GUID *guid);
-void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old,
- uint64_t new);
-
-/* Return version of FSP associated with fih. */
-static inline uint32_t fsp_version(FSP_INFO_HEADER *fih)
-{
- return fih->ImageRevision;
-}
-
-/*
- * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success.
- * The FSP source is pointed to by region_device and the relocation information
- * is encoded in a struct prog with its entry point set to the FSP info header.
- */
-int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
-
-/* Additional HOB types not included in the FSP:
- * #define EFI_HOB_TYPE_HANDOFF 0x0001
- * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
- * #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
- * #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
- * #define EFI_HOB_TYPE_FV 0x0005
- * #define EFI_HOB_TYPE_CPU 0x0006
- * #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
- * #define EFI_HOB_TYPE_CV 0x0008
- * #define EFI_HOB_TYPE_UNUSED 0xFFFE
- * #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff
- */
-#define EFI_HOB_TYPE_HANDOFF 0x0001
-#define EFI_HOB_TYPE_MEMORY_POOL 0x0007
-
-/* The offset in bytes from the start of the info structure */
-#define FSP_IMAGE_SIG_LOC 0
-#define FSP_IMAGE_ID_LOC 16
-#define FSP_IMAGE_BASE_LOC 28
-#define FSP_IMAGE_ATTRIBUTE_LOC 32
-#define GRAPHICS_SUPPORT_BIT (1 << 0)
-
-#define ERROR_NO_FV_SIG 1
-#define ERROR_NO_FFS_GUID 2
-#define ERROR_NO_INFO_HEADER 3
-#define ERROR_IMAGEBASE_MISMATCH 4
-#define ERROR_INFO_HEAD_SIG_MISMATCH 5
-#define ERROR_FSP_SIG_MISMATCH 6
-
-#if ENV_RAMSTAGE
-extern void *FspHobListPtr;
-#endif
-
-/* TODO: Remove the EFI types and decorations from coreboot implementations. */
-VOID * EFIAPI get_hob_list(VOID);
-VOID * EFIAPI get_next_hob(UINT16 type, CONST VOID *hob_start);
-VOID * EFIAPI get_first_hob(UINT16 type);
-VOID * EFIAPI get_next_guid_hob(CONST EFI_GUID * guid, CONST VOID *hob_start);
-VOID * EFIAPI get_first_guid_hob(CONST EFI_GUID * guid);
-
-#endif /* FSP1_1_UTIL_H */
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
deleted file mode 100644
index e505b93..0000000
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014-2016 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <console/console.h>
-#include <fsp/memmap.h>
-#include <fsp/romstage.h>
-#include <fsp/util.h>
-#include <lib.h> /* hexdump */
-#include <reset.h>
-#include <soc/intel/common/mma.h>
-#include <string.h>
-#include <timestamp.h>
-#include <bootmode.h>
-
-void raminit(struct romstage_params *params)
-{
- const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
- EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root;
- FSP_INFO_HEADER *fsp_header;
- EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory;
- FSP_MEMORY_INIT fsp_memory_init;
- FSP_MEMORY_INIT_PARAMS fsp_memory_init_params;
- const EFI_GUID fsp_reserved_guid =
- FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID;
- void *fsp_reserved_memory_area;
- FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer;
- void *hob_list_ptr;
- FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
- const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
- MEMORY_INIT_UPD memory_init_params;
- const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
- u32 *mrc_hob;
- u32 fsp_reserved_bytes;
- MEMORY_INIT_UPD *original_params;
- struct pei_data *pei_ptr;
- EFI_STATUS status;
- VPD_DATA_REGION *vpd_ptr;
- UPD_DATA_REGION *upd_ptr;
- int fsp_verification_failure = 0;
-#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
- unsigned long int data;
- EFI_PEI_HOB_POINTERS hob_ptr;
-#endif
-
- /*
- * Find and copy the UPD region to the stack so the platform can modify
- * the settings if needed. Modifications to the UPD buffer are done in
- * the platform callback code. The platform callback code is also
- * responsible for assigning the UpdDataRngPtr to this buffer if any
- * updates are made. The default state is to leave the UpdDataRngPtr
- * set to NULL. This indicates that the FSP code will use the UPD
- * region in the FSP binary.
- */
- post_code(0x34);
- fsp_header = params->chipset_context;
- vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
- fsp_header->ImageBase);
- printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr);
- upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
- fsp_header->ImageBase);
- printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr);
- original_params = (void *)((u8 *)upd_ptr +
- upd_ptr->MemoryInitUpdOffset);
- memcpy(&memory_init_params, original_params,
- sizeof(memory_init_params));
-
- /* Zero fill RT Buffer data and start populating fields. */
- memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer));
- pei_ptr = params->pei_data;
- if (pei_ptr->boot_mode == SLEEP_STATE_S3) {
- fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME;
- } else if (pei_ptr->saved_data != NULL) {
- fsp_rt_common_buffer.BootMode =
- BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
- } else {
- fsp_rt_common_buffer.BootMode = BOOT_WITH_FULL_CONFIGURATION;
- }
- fsp_rt_common_buffer.UpdDataRgnPtr = &memory_init_params;
- fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size();
-
- /* Get any board specific changes */
- fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data;
- fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer;
- fsp_memory_init_params.HobListPtr = &hob_list_ptr;
-
- /* Update the UPD data */
- soc_memory_init_params(params, &memory_init_params);
- mainboard_memory_init_params(params, &memory_init_params);
-
- if (IS_ENABLED(CONFIG_MMA))
- setup_mma(&memory_init_params);
-
- post_code(0x36);
-
- /* Display the UPD data */
- if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
- soc_display_memory_init_params(original_params,
- &memory_init_params);
-
- /* Call FspMemoryInit to initialize RAM */
- fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase
- + fsp_header->FspMemoryInitEntryOffset);
- printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init);
- printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n",
- fsp_memory_init_params.NvsBufferPtr);
- printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n",
- fsp_memory_init_params.RtBufferPtr);
- printk(BIOS_SPEW, " 0x%p: HobListPtr\n",
- fsp_memory_init_params.HobListPtr);
-
- timestamp_add_now(TS_FSP_MEMORY_INIT_START);
- post_code(POST_FSP_MEMORY_INIT);
- status = fsp_memory_init(&fsp_memory_init_params);
- post_code(0x37);
- timestamp_add_now(TS_FSP_MEMORY_INIT_END);
-
- printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
- if (status != EFI_SUCCESS)
- die("ERROR - FspMemoryInit failed to initialize memory!\n");
-
- /* Locate the FSP reserved memory area */
- fsp_reserved_bytes = 0;
- fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr);
- if (fsp_memory == NULL) {
- fsp_verification_failure = 1;
- printk(BIOS_DEBUG,
- "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n");
- } else {
- fsp_reserved_bytes = fsp_memory->ResourceLength;
- printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n",
- (unsigned long int)fsp_reserved_bytes);
- }
-
- /* Display SMM area */
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
- char *smm_base;
- size_t smm_size;
-
- smm_region((void **)&smm_base, &smm_size);
- printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size);
- printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base);
-#endif
-
- /* Migrate CAR data */
- printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
- if (pei_ptr->boot_mode != SLEEP_STATE_S3) {
- cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
- fsp_reserved_bytes);
- } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
- fsp_reserved_bytes)) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
- printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
- /* Failed S3 resume, reset to come up cleanly */
- hard_reset();
-#endif
- }
-
- /* Save the FSP runtime parameters. */
- fsp_set_runtime(fsp_header, hob_list_ptr);
-
- /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */
- cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr);
- if (cbmem_root == NULL) {
- fsp_verification_failure = 1;
- printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n");
- printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n",
- fsp_rt_common_buffer.BootLoaderTolumSize);
- }
-
- /* Locate the FSP_SMBIOS_MEMORY_INFO HOB */
- memory_info_hob = get_next_guid_hob(&memory_info_hob_guid,
- hob_list_ptr);
- if (NULL == memory_info_hob) {
- printk(BIOS_ERR, "FSP_SMBIOS_MEMORY_INFO HOB missing!\n");
- fsp_verification_failure = 1;
- } else {
- printk(BIOS_DEBUG,
- "FSP_SMBIOS_MEMORY_INFO HOB: 0x%p\n",
- memory_info_hob);
- }
-
-#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
- if (hob_list_ptr == NULL)
- die("ERROR - HOB pointer is NULL!\n");
-
- /*
- * Verify that FSP is generating the required HOBs:
- * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
- * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified above
- * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified below
- * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified above
- * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit
- * FSP_SMBIOS_MEMORY_INFO HOB verified above
- */
- if (NULL != cbmem_root) {
- printk(BIOS_DEBUG,
- "7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n",
- cbmem_root);
- data = cbmem_root->PhysicalStart;
- printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
- data = cbmem_root->ResourceLength;
- printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
- }
- hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr);
- if (NULL == hob_ptr.Raw) {
- printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n");
- fsp_verification_failure =
- (params->pei_data->saved_data == NULL) ? 1 : 0;
- } else {
- printk(BIOS_DEBUG,
- "7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n",
- hob_ptr.Raw);
- }
- if (fsp_memory != NULL) {
- printk(BIOS_DEBUG,
- "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n",
- fsp_memory);
- data = fsp_memory->PhysicalStart;
- printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
- data = fsp_memory->ResourceLength;
- printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
- }
-
- /* Verify all the HOBs are present */
- if (fsp_verification_failure)
- printk(BIOS_DEBUG,
- "ERROR - Missing one or more required FSP HOBs!\n");
-
- /* Display the HOBs */
- print_hob_type_structure(0, hob_list_ptr);
-#endif
-
- /* Get the address of the CBMEM region for the FSP reserved memory */
- fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
- printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n",
- fsp_reserved_memory_area);
-
- /* Verify the order of CBMEM root and FSP memory */
- if ((fsp_memory != NULL) && (cbmem_root != NULL) &&
- (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) {
- fsp_verification_failure = 1;
- printk(BIOS_DEBUG,
- "ERROR - FSP reserved memory above CBMEM root!\n");
- }
-
- /* Verify that the FSP memory was properly reserved */
- if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) ||
- (fsp_memory->PhysicalStart !=
- (unsigned int)fsp_reserved_memory_area))) {
- fsp_verification_failure = 1;
- printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n");
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
- if (cbmem_root != NULL) {
- size_t delta_bytes = (unsigned int)smm_base
- - cbmem_root->PhysicalStart
- - cbmem_root->ResourceLength;
- printk(BIOS_DEBUG,
- "0x%08x: Chipset reserved bytes reported by FSP\n",
- (unsigned int)delta_bytes);
- die("Please verify the chipset reserved size\n");
- }
-#endif
- }
-
- /* Verify the FSP 1.1 HOB interface */
- if (fsp_verification_failure)
- die("ERROR - Coreboot's requirements not met by FSP binary!\n");
-
- /* Display the memory configuration */
- report_memory_config();
-
- /* Locate the memory configuration data to speed up the next reboot */
- mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr);
- if (mrc_hob == NULL)
- printk(BIOS_DEBUG,
- "Memory Configuration Data Hob not present\n");
- else if (!recovery_mode_enabled()) {
- /* Do not save MRC data in recovery path */
- pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob);
- pei_ptr->data_to_save_size = ALIGN(
- ((u32)GET_HOB_LENGTH(mrc_hob)), 16);
- }
-}
-
-/* Initialize the UPD parameters for MemoryInit */
-__attribute__((weak)) void mainboard_memory_init_params(
- struct romstage_params *params,
- MEMORY_INIT_UPD *upd_ptr)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* Display the UPD parameters for MemoryInit */
-__attribute__((weak)) void soc_display_memory_init_params(
- const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new)
-{
- printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
- hexdump32(BIOS_SPEW, new, sizeof(*new));
-}
-
-/* Initialize the UPD parameters for MemoryInit */
-__attribute__((weak)) void soc_memory_init_params(
- struct romstage_params *params,
- MEMORY_INIT_UPD *upd)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
deleted file mode 100644
index 834f148..0000000
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <bootmode.h>
-#include <arch/acpi.h>
-#include <cbmem.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <fsp/memmap.h>
-#include <fsp/ramstage.h>
-#include <fsp/util.h>
-#include <lib.h>
-#include <stage_cache.h>
-#include <string.h>
-#include <timestamp.h>
-
-/* SOC initialization after FSP silicon init */
-__attribute__((weak)) void soc_after_silicon_init(void)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* Display SMM memory map */
-static void smm_memory_map(void)
-{
- void *base;
- size_t size;
- int i;
-
- printk(BIOS_SPEW, "SMM Memory Map\n");
-
- smm_region(&base, &size);
- printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size);
-
- for (i = 0; i < SMM_SUBREGION_NUM; i++) {
- if (smm_subregion(i, &base, &size))
- continue;
- printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size);
- }
-}
-
-static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
-{
- const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
- int missing_hob = 0;
- void *hob_list_ptr = get_hob_list();
-
- if (!IS_ENABLED(CONFIG_DISPLAY_HOBS))
- return;
-
- /* Verify the HOBs */
- if (hob_list_ptr == NULL) {
- printk(BIOS_INFO, "ERROR - HOB pointer is NULL!\n");
- return;
- }
-
- print_hob_type_structure(0, hob_list_ptr);
-
- /*
- * Verify that FSP is generating the required HOBs:
- * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
- * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit
- * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit
- * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit
- * 7.5: EFI_PEI_GRAPHICS_INFO_HOB verified below,
- * if the ImageAttribute bit is set
- * FSP_SMBIOS_MEMORY_INFO HOB verified by raminit
- */
- if ((fsp_info_header->ImageAttribute & GRAPHICS_SUPPORT_BIT) &&
- !get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) {
- printk(BIOS_INFO, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n");
- missing_hob = 1;
- }
-
- if (missing_hob)
- printk(BIOS_INFO,
- "ERROR - Missing one or more required FSP HOBs!\n");
-}
-
-void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
-{
- FSP_SILICON_INIT fsp_silicon_init;
- SILICON_INIT_UPD *original_params;
- SILICON_INIT_UPD silicon_init_params;
- EFI_STATUS status;
- UPD_DATA_REGION *upd_ptr;
- VPD_DATA_REGION *vpd_ptr;
-
- /* Display the FSP header */
- if (fsp_info_header == NULL) {
- printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
- return;
- }
- print_fsp_info(fsp_info_header);
-
- /* Initialize the UPD values */
- vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset +
- fsp_info_header->ImageBase);
- printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr);
- upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
- fsp_info_header->ImageBase);
- printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr);
- original_params = (void *)((u8 *)upd_ptr +
- upd_ptr->SiliconInitUpdOffset);
- memcpy(&silicon_init_params, original_params,
- sizeof(silicon_init_params));
- soc_silicon_init_params(&silicon_init_params);
-
- /* Locate VBT and pass to FSP GOP */
- if (IS_ENABLED(CONFIG_GOP_SUPPORT))
- load_vbt(is_s3_wakeup, &silicon_init_params);
- mainboard_silicon_init_params(&silicon_init_params);
-
- /* Display the UPD data */
- if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
- soc_display_silicon_init_params(original_params,
- &silicon_init_params);
-
- /* Perform silicon initialization after RAM is configured */
- printk(BIOS_DEBUG, "Calling FspSiliconInit\n");
- fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase
- + fsp_info_header->FspSiliconInitEntryOffset);
- timestamp_add_now(TS_FSP_SILICON_INIT_START);
- printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n",
- &silicon_init_params, fsp_silicon_init);
- post_code(POST_FSP_SILICON_INIT);
- status = fsp_silicon_init(&silicon_init_params);
- timestamp_add_now(TS_FSP_SILICON_INIT_END);
- printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
-
- /* Mark graphics init done after SiliconInit if VBT was provided */
-#if IS_ENABLED(CONFIG_GOP_SUPPORT)
- /* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs
- * to be #if'd out instead of using if(). */
- if (silicon_init_params.GraphicsConfigPtr)
- gfx_set_init_done(1);
-#endif
-
- display_hob_info(fsp_info_header);
- soc_after_silicon_init();
-}
-
-static void fsp_cache_save(struct prog *fsp)
-{
- if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP))
- smm_memory_map();
-
- if (prog_entry(fsp) == NULL) {
- printk(BIOS_ERR, "ERROR: No FSP to save in cache.\n");
- return;
- }
-
- stage_cache_add(STAGE_REFCODE, fsp);
-}
-
-static int fsp_find_and_relocate(struct prog *fsp)
-{
- if (prog_locate(fsp)) {
- printk(BIOS_ERR, "ERROR: Couldn't find %s\n", prog_name(fsp));
- return -1;
- }
-
- if (fsp_relocate(fsp, prog_rdev(fsp))) {
- printk(BIOS_ERR, "ERROR: FSP relocation failed.\n");
- return -1;
- }
-
- return 0;
-}
-
-void intel_silicon_init(void)
-{
- struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
- int is_s3_wakeup = acpi_is_wakeup_s3();
-
- if (is_s3_wakeup) {
- printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
- stage_cache_load_stage(STAGE_REFCODE, &fsp);
- } else {
- fsp_find_and_relocate(&fsp);
- printk(BIOS_DEBUG, "FSP: Saving binary in cache\n");
- fsp_cache_save(&fsp);
- }
-
- /* FSP_INFO_HEADER is set as the program entry. */
- fsp_update_fih(prog_entry(&fsp));
-
- fsp_run_silicon_init(fsp_get_fih(), is_s3_wakeup);
-}
-
-/* Initialize the UPD parameters for SiliconInit */
-__attribute__((weak)) void mainboard_silicon_init_params(
- SILICON_INIT_UPD *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-};
-
-/* Display the UPD parameters for SiliconInit */
-__attribute__((weak)) void soc_display_silicon_init_params(
- const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
-{
- printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
- hexdump32(BIOS_SPEW, new, sizeof(*new));
-}
-
-/* Initialize the UPD parameters for SiliconInit */
-__attribute__((weak)) void soc_silicon_init_params(SILICON_INIT_UPD *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
deleted file mode 100644
index 3d698bb..0000000
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ /dev/null
@@ -1,420 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stddef.h>
-#include <arch/io.h>
-#include <arch/cbfs.h>
-#include <arch/stages.h>
-#include <arch/early_variables.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <cbmem.h>
-#include <cpu/intel/microcode.h>
-#include <cpu/x86/mtrr.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <elog.h>
-#include <fsp/romstage.h>
-#include <reset.h>
-#include <romstage_handoff.h>
-#include <smbios.h>
-#include <soc/intel/common/mrc_cache.h>
-#include <stage_cache.h>
-#include <timestamp.h>
-#include <tpm.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
-{
- void *top_of_stack;
- struct pei_data pei_data;
- struct romstage_params params = {
- .pei_data = &pei_data,
- .chipset_context = fih,
- };
-
- post_code(0x30);
-
- timestamp_add_now(TS_START_ROMSTAGE);
-
- /* Load microcode before ram init */
- if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
- intel_update_microcode_from_cbfs();
-
- memset(&pei_data, 0, sizeof(pei_data));
-
- /* Display parameters */
- printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
- CONFIG_MMCONF_BASE_ADDRESS);
- printk(BIOS_INFO, "Using FSP 1.1\n");
-
- /* Display FSP banner */
- print_fsp_info(fih);
-
- /* Stash FSP version. */
- params.fsp_version = fsp_version(fih);
-
- /* Get power state */
- params.power_state = fill_power_state();
-
- /*
- * Read and print board version. Done after SOC romstage
- * in case PCH needs to be configured to talk to the EC.
- */
- if (IS_ENABLED(CONFIG_BOARD_ID_AUTO))
- printk(BIOS_INFO, "MLB: board version %d\n", board_id());
-
- /* Call into mainboard. */
- mainboard_romstage_entry(¶ms);
- soc_after_ram_init(¶ms);
- post_code(0x38);
-
- top_of_stack = setup_stack_and_mtrrs();
-
- printk(BIOS_DEBUG, "Calling FspTempRamExit API\n");
- timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START);
- return top_of_stack;
-}
-
-void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
-{
- return romstage_main(fih);
-}
-
-/* Entry from the mainboard. */
-void romstage_common(struct romstage_params *params)
-{
- const struct mrc_saved_data *cache;
- struct romstage_handoff *handoff;
- struct pei_data *pei_data;
-
- post_code(0x32);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- pei_data = params->pei_data;
- pei_data->boot_mode = params->power_state->prev_sleep_state;
-
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
- if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
- boot_count_increment();
-#endif
-
- /* Perform remaining SOC initialization */
- soc_pre_ram_init(params);
- post_code(0x33);
-
- /* Check recovery and MRC cache */
- params->pei_data->saved_data_size = 0;
- params->pei_data->saved_data = NULL;
- if (!params->pei_data->disable_saved_data) {
- if (recovery_mode_enabled()) {
- /* Recovery mode does not use MRC cache */
- printk(BIOS_DEBUG,
- "Recovery mode: not using MRC cache.\n");
- } else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)
- && (!mrc_cache_get_current_with_version(&cache,
- params->fsp_version))) {
- /* MRC cache found */
- params->pei_data->saved_data_size = cache->size;
- params->pei_data->saved_data = &cache->data[0];
- } else if (params->pei_data->boot_mode == SLEEP_STATE_S3) {
- /* Waking from S3 and no cache. */
- printk(BIOS_DEBUG,
- "No MRC cache found in S3 resume path.\n");
- post_code(POST_RESUME_FAILURE);
- hard_reset();
- } else {
- printk(BIOS_DEBUG, "No MRC cache found.\n");
- mainboard_check_ec_image(params);
- }
- }
-
- /* Initialize RAM */
- raminit(params);
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Save MRC output */
- if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {
- printk(BIOS_DEBUG, "MRC data at %p %d bytes\n",
- pei_data->data_to_save, pei_data->data_to_save_size);
- if ((params->pei_data->boot_mode != SLEEP_STATE_S3)
- && (params->pei_data->data_to_save_size != 0)
- && (params->pei_data->data_to_save != NULL))
- mrc_cache_stash_data_with_version(
- params->pei_data->data_to_save,
- params->pei_data->data_to_save_size,
- params->fsp_version);
- }
-
- /* Save DIMM information */
- mainboard_save_dimm_info(params);
-
- /* Create romstage handof information */
- handoff = romstage_handoff_find_or_add();
- if (handoff != NULL)
- handoff->s3_resume = (params->power_state->prev_sleep_state ==
- SLEEP_STATE_S3);
- else {
- printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
- hard_reset();
- }
-
- /*
- * Initialize the TPM, unless the TPM was already initialized
- * in verstage and used to verify romstage.
- */
- if (IS_ENABLED(CONFIG_LPC_TPM) &&
- !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&
- !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
- init_tpm(params->power_state->prev_sleep_state ==
- SLEEP_STATE_S3);
-}
-
-void after_cache_as_ram_stage(void)
-{
- /* Load the ramstage. */
- copy_and_run();
- die("ERROR - Failed to load ramstage!");
-}
-
-/* Initialize the power state */
-__attribute__((weak)) struct chipset_power_state *fill_power_state(void)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
- return NULL;
-}
-
-__attribute__((weak)) void mainboard_check_ec_image(
- struct romstage_params *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
- struct pei_data *pei_data;
-
- pei_data = params->pei_data;
- if (params->pei_data->boot_mode == SLEEP_STATE_S0) {
- /* Ensure EC is running RO firmware. */
- google_chromeec_check_ec_image(EC_IMAGE_RO);
- }
-#endif
-}
-
-/* Board initialization before and after RAM is enabled */
-__attribute__((weak)) void mainboard_romstage_entry(
- struct romstage_params *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-
- post_code(0x31);
-
- /* Initliaze memory */
- romstage_common(params);
-}
-
-/* Save the DIMM information for SMBIOS table 17 */
-__attribute__((weak)) void mainboard_save_dimm_info(
- struct romstage_params *params)
-{
- int channel;
- CHANNEL_INFO *channel_info;
- int dimm;
- DIMM_INFO *dimm_info;
- int dimm_max;
- void *hob_list_ptr;
- EFI_HOB_GUID_TYPE *hob_ptr;
- int index;
- struct memory_info *mem_info;
- FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
- const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
-
- /* Locate the memory info HOB, presence validated by raminit */
- hob_list_ptr = fsp_get_hob_list();
- hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr);
- memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1);
-
- /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */
- if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) {
- printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n");
- printk(BIOS_DEBUG, " 0x%02x: Revision\n",
- memory_info_hob->Revision);
- printk(BIOS_DEBUG, " 0x%02x: MemoryType\n",
- memory_info_hob->MemoryType);
- printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n",
- memory_info_hob->MemoryFrequencyInMHz);
- printk(BIOS_DEBUG, " %d: DataWidth in bits\n",
- memory_info_hob->DataWidth);
- printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n",
- memory_info_hob->ErrorCorrectionType);
- printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n",
- memory_info_hob->ChannelCount);
- for (channel = 0; channel < memory_info_hob->ChannelCount;
- channel++) {
- channel_info = &memory_info_hob->ChannelInfo[channel];
- printk(BIOS_DEBUG, " Channel %d\n", channel);
- printk(BIOS_DEBUG, " 0x%02x: ChannelId\n",
- channel_info->ChannelId);
- printk(BIOS_DEBUG, " 0x%02x: DimmCount\n",
- channel_info->DimmCount);
- for (dimm = 0; dimm < channel_info->DimmCount;
- dimm++) {
- dimm_info = &channel_info->DimmInfo[dimm];
- printk(BIOS_DEBUG, " DIMM %d\n", dimm);
- printk(BIOS_DEBUG, " 0x%02x: DimmId\n",
- dimm_info->DimmId);
- printk(BIOS_DEBUG, " %d: SizeInMb\n",
- dimm_info->SizeInMb);
- }
- }
- }
-
- /*
- * Allocate CBMEM area for DIMM information used to populate SMBIOS
- * table 17
- */
- mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
- printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);
- if (mem_info == NULL)
- return;
- memset(mem_info, 0, sizeof(*mem_info));
-
- /* Describe the first N DIMMs in the system */
- index = 0;
- dimm_max = ARRAY_SIZE(mem_info->dimm);
- for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) {
- if (index >= dimm_max)
- break;
- channel_info = &memory_info_hob->ChannelInfo[channel];
- for (dimm = 0; dimm < channel_info->DimmCount; dimm++) {
- if (index >= dimm_max)
- break;
- dimm_info = &channel_info->DimmInfo[dimm];
-
- /* Populate the DIMM information */
- if (dimm_info->SizeInMb) {
- mem_info->dimm[index].dimm_size =
- dimm_info->SizeInMb;
- mem_info->dimm[index].ddr_type =
- memory_info_hob->MemoryType;
- mem_info->dimm[index].ddr_frequency =
- memory_info_hob->MemoryFrequencyInMHz;
- mem_info->dimm[index].channel_num =
- channel_info->ChannelId;
- mem_info->dimm[index].dimm_num =
- dimm_info->DimmId;
- switch (memory_info_hob->DataWidth) {
- default:
- case 8:
- mem_info->dimm[index].bus_width =
- MEMORY_BUS_WIDTH_8;
- break;
-
- case 16:
- mem_info->dimm[index].bus_width =
- MEMORY_BUS_WIDTH_16;
- break;
-
- case 32:
- mem_info->dimm[index].bus_width =
- MEMORY_BUS_WIDTH_32;
- break;
-
- case 64:
- mem_info->dimm[index].bus_width =
- MEMORY_BUS_WIDTH_64;
- break;
-
- case 128:
- mem_info->dimm[index].bus_width =
- MEMORY_BUS_WIDTH_128;
- break;
- }
-
- /* Add any mainboard specific information */
- mainboard_add_dimm_info(params, mem_info,
- channel, dimm, index);
- index++;
- }
- }
- }
- mem_info->dimm_cnt = index;
- printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
-}
-
-/* Add any mainboard specific information */
-__attribute__((weak)) void mainboard_add_dimm_info(
- struct romstage_params *params,
- struct memory_info *mem_info,
- int channel, int dimm, int index)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* Get the memory configuration data */
-__attribute__((weak)) int mrc_cache_get_current(
- const struct mrc_saved_data **cache)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
- return -1;
-}
-
-/* Save the memory configuration data */
-__attribute__((weak)) int mrc_cache_stash_data(void *data, size_t size)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
- return -1;
-}
-
-/* Transition RAM from off or self-refresh to active */
-__attribute__((weak)) void raminit(struct romstage_params *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
- post_code(0x34);
- die("ERROR - No RAM initialization specified!\n");
-}
-
-void ramstage_cache_invalid(void)
-{
- if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE))
- /* Perform cold reset on invalid ramstage cache. */
- hard_reset();
-}
-
-/* Display the memory configuration */
-__attribute__((weak)) void report_memory_config(void)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* Choose top of stack and setup MTRRs */
-__attribute__((weak)) void *setup_stack_and_mtrrs(void)
-{
- printk(BIOS_ERR, "WEAK: %s/%s called\n", __FILE__, __func__);
- die("ERROR - Must specify top of stack!\n");
- return NULL;
-}
-
-/* SOC initialization after RAM is enabled */
-__attribute__((weak)) void soc_after_ram_init(struct romstage_params *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* SOC initialization before RAM is enabled */
-__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
diff --git a/src/drivers/intel/fsp1_1/romstage_after_verstage.S b/src/drivers/intel/fsp1_1/romstage_after_verstage.S
deleted file mode 100644
index 739db29..0000000
--- a/src/drivers/intel/fsp1_1/romstage_after_verstage.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
-
-.text
-.global _start
-_start:
- /* This is the romstage entry point when CONFIG_SEPARATE_VERSTAGE
- * is used. The stack, descriptors, and gdt are already initialized
- * by verstage. However, in order to maintain the semantics of
- * CAR_GLOBAL variables we need to clear those to zero. */
- cld
- xor %eax, %eax
- movl $(_car_global_end), %ecx
- movl $(_car_global_start), %edi
- sub %edi, %ecx
- rep stosl
- call romstage_after_verstage
- #include "after_raminit.S"
-
- movb $0x69, %ah
- jmp .Lhlt
-
-.Lhlt:
- xchg %al, %ah
-#if IS_ENABLED(CONFIG_POST_IO)
- outb %al, $CONFIG_POST_IO_PORT
-#else
- post_code(POST_DEAD_CODE)
-#endif
- movl $LHLT_DELAY, %ecx
-.Lhlt_Delay:
- outb %al, $0xED
- loop .Lhlt_Delay
- jmp .Lhlt
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
deleted file mode 100644
index e048229..0000000
--- a/src/drivers/intel/fsp1_1/stack.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <console/console.h>
-#include <cpu/x86/mtrr.h>
-#include <fsp/memmap.h>
-#include <fsp/romstage.h>
-#include <fsp/stack.h>
-#include <stdlib.h>
-
-const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;
-
-/*
- * Romstage needs quite a bit of stack for decompressing images since the lzma
- * lib keeps its state on the stack during romstage.
- */
-static unsigned long choose_top_of_stack(void)
-{
- unsigned long stack_top;
-
- /* cbmem_add() does a find() before add(). */
- stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
- romstage_ram_stack_size);
- stack_top += romstage_ram_stack_size;
- return stack_top;
-}
-
-/*
- * setup_stack_and_mtrrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use.
- */
-void *setup_stack_and_mtrrs(void)
-{
- size_t alignment;
- uint32_t aligned_ram;
- uint32_t mtrr_mask_upper;
- uint32_t max_mtrrs;
- uint32_t num_mtrrs;
- uint32_t *slot;
- unsigned long top_of_stack;
-
- /* Display the MTTRs */
- soc_display_mtrrs();
-
- /* Top of stack needs to be aligned to a 8-byte boundary. */
- top_of_stack = choose_top_of_stack();
- slot = (void *)top_of_stack;
- num_mtrrs = 0;
- max_mtrrs = soc_get_variable_mtrr_count(NULL);
-
- /*
- * The upper bits of the MTRR mask need to set according to the number
- * of physical address bits.
- */
- mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
- alignment = mmap_region_granularity();
- aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size,
- alignment);
-
- /*
- * The order for each MTRR is value then base with upper 32-bits of
- * each value coming before the lower 32-bits. The reasoning for
- * this ordering is to create a stack layout like the following:
- *
- * +36: MTRR mask 1 63:32
- * +32: MTRR mask 1 31:0
- * +28: MTRR base 1 63:32
- * +24: MTRR base 1 31:0
- * +20: MTRR mask 0 63:32
- * +16: MTRR mask 0 31:0
- * +12: MTRR base 0 63:32
- * +8: MTRR base 0 31:0
- * +4: Number of MTRRs to setup (described above)
- * +0: Number of variable MTRRs to clear
- */
-
- /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
- slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push32(slot, 0); /* upper base */
- slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-
- /*
- * +-------------------------+ Top of RAM (aligned)
- * | System Management Mode |
- * | code and data | Length: CONFIG_TSEG_SIZE
- * | (TSEG) |
- * +-------------------------+ SMM base (aligned)
- * | |
- * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE
- * | |
- * +-------------------------+ top_of_ram (aligned)
- * | |
- * | CBMEM Root |
- * | |
- * +-------------------------+
- * | |
- * | FSP Reserved Memory |
- * | |
- * +-------------------------+
- * | |
- * | Various CBMEM Entries |
- * | |
- * +-------------------------+ top_of_stack (8 byte aligned)
- * | |
- * | stack (CBMEM Entry) |
- * | |
- * +-------------------------+
- */
-
- /*
- * Cache the stack and the other CBMEM entries as well as part or all
- * of the FSP reserved memory region.
- */
- slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push32(slot, 0); /* upper base */
- slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
- void *smm_base;
- size_t smm_size;
- uint32_t tseg_base;
-
- /*
- * Cache the TSEG region at the top of ram. This region is not
- * restricted to SMM mode until SMM has been relocated. By setting
- * the region to cacheable it provides faster access when relocating
- * the SMM handler as well as using the TSEG region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- tseg_base = (uint32_t)smm_base;
- slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push32(slot, 0); /* upper base */
- slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-#endif
-
- /* Cache the ROM as WP just below 4GiB. */
- slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push32(slot, 0); /* upper base */
- slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
- num_mtrrs++;
-
- /* Validate the MTRR usage */
- if (num_mtrrs > max_mtrrs) {
- printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d",
- max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs);
- die("ERROR - MTRR use count incorrect!\n");
- }
-
- /*
- * Save the number of MTRRs to setup and clear. Return the stack
- * location pointing to the number of MTRRs.
- */
- slot = stack_push32(slot, num_mtrrs);
- slot = stack_push32(slot, max_mtrrs);
- return slot;
-}
-
diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c
deleted file mode 100644
index 2d594e6..0000000
--- a/src/drivers/intel/fsp1_1/stage_cache.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <fsp/memmap.h>
-#include <stage_cache.h>
-
-void stage_cache_external_region(void **base, size_t *size)
-{
- if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
- printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
- *base = NULL;
- *size = 0;
- }
-}
diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c
deleted file mode 100644
index 414b88d..0000000
--- a/src/drivers/intel/fsp1_1/vbt.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <bootmode.h>
-#include <console/console.h>
-#include <fsp/ramstage.h>
-#include <fsp/util.h>
-
-/* Locate VBT and pass it to FSP GOP */
-void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
-{
- const optionrom_vbt_t *vbt_data = NULL;
- uint32_t vbt_len;
-
- /* Check boot mode - for S3 resume path VBT loading is not needed */
- if (s3_resume) {
- printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n");
- } else if (display_init_required()) {
- /* Get VBT data */
- vbt_data = fsp_get_vbt(&vbt_len);
- if (vbt_data != NULL)
- printk(BIOS_DEBUG, "Passing VBT to GOP\n");
- else
- printk(BIOS_DEBUG, "VBT not found!\n");
- } else {
- printk(BIOS_DEBUG, "Not passing VBT to GOP\n");
- }
- params->GraphicsConfigPtr = (u32)vbt_data;
-}
diff --git a/src/drivers/intel/fsp1_1/verstage.c b/src/drivers/intel/fsp1_1/verstage.c
deleted file mode 100644
index d7cdfdf..0000000
--- a/src/drivers/intel/fsp1_1/verstage.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <fsp/car.h>
-#include <program_loading.h>
-
-void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
-{
- run_romstage();
- /* Will actually never return. */
- return NULL;
-}
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
deleted file mode 100644
index 19e04f7..0000000
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-config PLATFORM_USES_FSP2_0
- bool
- help
- Include FSP 2.0 wrappers and functionality
-
-
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
deleted file mode 100644
index 3e94f2f..0000000
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
-
-romstage-y += hand_off_block.c
-romstage-y += util.c
-romstage-y += memory_init.c
-
-ramstage-y += graphics.c
-ramstage-y += hand_off_block.c
-ramstage-y += notify.c
-ramstage-y += silicon_init.c
-ramstage-y += util.c
-
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
-
-endif
diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c
deleted file mode 100644
index 1480179..0000000
--- a/src/drivers/intel/fsp2_0/graphics.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <cbfs.h>
-#include <console/console.h>
-#include <fsp/util.h>
-
-enum pixel_format {
- pixel_rgbx_8bpc = 0,
- pixel_bgrx_8bpc = 1,
- pixel_bitmask = 2, /* defined by <rgb>_mask values */
-};
-
-static const uint8_t uuid_graphics_info[16] = {
- 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46,
- 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07
-};
-
-struct hob_graphics_info {
- uint64_t framebuffer_base;
- uint32_t framebuffer_size;
- uint32_t version;
- uint32_t horizontal_resolution;
- uint32_t vertical_resolution;
- uint32_t pixel_format; /* See enum pixel_format */
- uint32_t red_mask;
- uint32_t green_mask;
- uint32_t blue_mask;
- uint32_t reserved_mask;
- uint32_t pixels_per_scanline;
-} __attribute__((packed));
-
-struct pixel {
- uint8_t pos;
- uint8_t size;
-};
-
-static const struct fsp_framebuffer {
- struct pixel red;
- struct pixel green;
- struct pixel blue;
- struct pixel rsvd;
-} fsp_framebuffer_format_map[] = {
- [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
- [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
-};
-
-enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
-{
- size_t size;
- const struct hob_graphics_info *ginfo;
- const struct fsp_framebuffer *fbinfo;
-
- ginfo = fsp_find_extension_hob_by_uuid(uuid_graphics_info, &size);
-
- if (!ginfo) {
- printk(BIOS_ALERT, "Graphics hand-off block not found\n");
- return CB_ERR;
- }
-
- if (ginfo->pixel_format > ARRAY_SIZE(fsp_framebuffer_format_map)) {
- printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n",
- ginfo->pixel_format);
- return CB_ERR;
- }
-
- fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format;
-
- framebuffer->physical_address = ginfo->framebuffer_base;
- framebuffer->x_resolution = ginfo->horizontal_resolution;
- framebuffer->y_resolution = ginfo->vertical_resolution;
- framebuffer->bytes_per_line = ginfo->pixels_per_scanline * 4;
- framebuffer->bits_per_pixel = 32;
- framebuffer->red_mask_pos = fbinfo->red.pos;
- framebuffer->red_mask_size = fbinfo->red.size;
- framebuffer->green_mask_pos = fbinfo->green.pos;
- framebuffer->green_mask_size = fbinfo->green.size;
- framebuffer->blue_mask_pos = fbinfo->blue.pos;
- framebuffer->blue_mask_size = fbinfo->blue.size;
- framebuffer->reserved_mask_pos = fbinfo->rsvd.pos;
- framebuffer->reserved_mask_size = fbinfo->rsvd.pos;
- framebuffer->tag = LB_TAG_FRAMEBUFFER;
- framebuffer->size = sizeof(*framebuffer);
- return CB_SUCCESS;
-}
-
-uintptr_t fsp_load_vbt(void)
-{
- void *vbt;
-
- vbt = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, NULL);
- if (!vbt)
- printk(BIOS_NOTICE, "Could not locate a VBT file in CBFS\n");
-
- return (uintptr_t)vbt;
-}
diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c
deleted file mode 100644
index 00c5d26..0000000
--- a/src/drivers/intel/fsp2_0/hand_off_block.c
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <arch/io.h>
-#include <cbmem.h>
-#include <commonlib/helpers.h>
-#include <console/console.h>
-#include <fsp/util.h>
-#include <inttypes.h>
-#include <lib.h>
-#include <string.h>
-
-#define HOB_HEADER_LEN 8
-
-struct hob_header {
- uint16_t type;
- uint16_t length;
-} __attribute__((packed));
-
-struct hob_resource {
- uint8_t owner_guid[16];
- uint32_t type;
- uint32_t attribute_type;
- uint64_t addr;
- uint64_t length;
-} __attribute__((packed));
-
-enum resource_type {
- EFI_RESOURCE_SYSTEM_MEMORY = 0,
- EFI_RESOURCE_MEMORY_MAPPED_IO = 1,
- EFI_RESOURCE_IO = 2,
- EFI_RESOURCE_FIRMWARE_DEVICE = 3,
- EFI_RESOURCE_MEMORY_MAPPED_IO_PORT = 4,
- EFI_RESOURCE_MEMORY_RESERVED = 5,
- EFI_RESOURCE_IO_RESERVED = 6,
- EFI_RESOURCE_MAX_MEMORY_TYPE = 7,
-};
-
-static const char *resource_names[] = {
- [EFI_RESOURCE_SYSTEM_MEMORY] = "SYSTEM_MEMORY",
- [EFI_RESOURCE_MEMORY_MAPPED_IO] = "MMIO",
- [EFI_RESOURCE_IO] = "IO",
- [EFI_RESOURCE_FIRMWARE_DEVICE] = "FIRMWARE_DEVICE",
- [EFI_RESOURCE_MEMORY_MAPPED_IO_PORT] = "MMIO_PORT",
- [EFI_RESOURCE_MEMORY_RESERVED] = "MEMORY_RESERVED",
- [EFI_RESOURCE_IO_RESERVED] = "IO_RESERVED",
-};
-
-enum hob_type {
- HOB_TYPE_HANDOFF = 0x0001,
- HOB_TYPE_MEMORY_ALLOCATION = 0x0002,
- HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003,
- HOB_TYPE_GUID_EXTENSION = 0x0004,
- HOB_TYPE_FV = 0x0005,
- HOB_TYPE_CPU = 0x0006,
- HOB_TYPE_MEMORY_POOL = 0x0007,
- HOB_TYPE_FV2 = 0x0009,
- HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A,
- HOB_TYPE_UCAPSULE = 0x000B,
- HOB_TYPE_UNUSED = 0xFFFE,
- HOB_TYPE_END_OF_HOB_LIST = 0xFFFF,
-};
-
-/* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */
-static const uint8_t uuid_owner_bootloader_tolum[16] = {
- 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44,
- 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44,
-};
-
-static const uint8_t uuid_owner_fsp[16] = {
- 0x59, 0x97, 0xa7, 0x69, 0x73, 0x13, 0x67, 0x43,
- 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e,
-};
-
-static const uint8_t uuid_owner_tseg[16] = {
- 0x7c, 0x74, 0x38, 0xd0, 0x0c, 0xd0, 0x80, 0x49,
- 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55
-};
-
-static const uint8_t uuid_fsp_nv_storage[16] = {
- 0x02, 0xcf, 0x1a, 0x72, 0x77, 0x4d, 0x2a, 0x4c,
- 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0
-};
-
-static const uint8_t empty_uuid[16] = {
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-static const struct uuid_name_map {
- const void *uuid;
- const char *name;
-} uuid_names[] = {
- { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" },
- { uuid_owner_fsp, "FSP_RESERVED_MEMORY" },
- { uuid_owner_tseg, "TSEG" },
- { uuid_fsp_nv_storage, "FSP_NV_STORAGE" },
-};
-
-static const char *resource_name(enum resource_type type)
-{
- if (type >= ARRAY_SIZE(resource_names))
- return "UNKNOWN";
- return resource_names[type];
-}
-
-/*
- * Utilities for walking HOBs
- */
-
-static bool uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16])
-{
- return !memcmp(uuid1, uuid2, 16);
-}
-
-static const char *uuid_name(const uint8_t uuid[16])
-{
- size_t i;
- const struct uuid_name_map *owner_entry;
-
- for (i = 0; i < ARRAY_SIZE(uuid_names); i++) {
- owner_entry = uuid_names + i;
- if (uuid_compare(uuid, owner_entry->uuid))
- return owner_entry->name;
- }
- return "UNKNOWN";
-}
-
-static const struct hob_header *next_hob(const struct hob_header *parent)
-{
- union {
- const struct hob_header *hob;
- uintptr_t addr;
- } hob_walker;
-
- hob_walker.hob = parent;
- hob_walker.addr += parent->length;
- return hob_walker.hob;
-}
-
-static const void *hob_header_to_struct(const struct hob_header *hob)
-{
- union {
- const struct hob_header *hob_hdr;
- const void *hob_descr;
- uintptr_t addr;
- } hob_walker;
-
- hob_walker.hob_hdr = hob;
- hob_walker.addr += HOB_HEADER_LEN;
- return hob_walker.hob_descr;
-}
-
-static const void *hob_header_to_extension_hob(const struct hob_header *hob)
-{
- union {
- const struct hob_header *hob_hdr;
- const void *hob_descr;
- uintptr_t addr;
- } hob_walker;
-
- hob_walker.hob_hdr = hob;
- hob_walker.addr += HOB_HEADER_LEN + 16; /* header and 16-byte UUID */
- return hob_walker.hob_descr;
-}
-
-static const
-struct hob_resource *hob_header_to_resource(const struct hob_header *hob)
-{
- return hob_header_to_struct(hob);
-}
-
-/*
- * Utilities for locating and identifying HOBs
- */
-
-void fsp_save_hob_list(void *hob_list_ptr)
-{
- void **cbmem_loc;
- cbmem_loc = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*hob_list_ptr));
- *cbmem_loc = hob_list_ptr;
-}
-
-const void *fsp_get_hob_list(void)
-{
- void **list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME);
-
- return (list_loc) ? (*list_loc) : NULL;
-}
-
-static const
-struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob,
- const uint8_t uuid[16])
-{
- const struct hob_resource *res;
-
- for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) {
-
- if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)
- continue;
-
- res = hob_header_to_resource(hob);
- if (uuid_compare(res->owner_guid, uuid))
- return res;
- }
- return NULL;
-}
-
-void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list)
-{
- const struct hob_resource *fsp_mem;
-
- range_entry_init(re, 0, 0, 0);
-
- fsp_mem = find_resource_hob_by_uuid(hob_list, uuid_owner_fsp);
-
- if (!fsp_mem) {
- return;
- }
-
- range_entry_init(re, fsp_mem->addr, fsp_mem->addr + fsp_mem->length, 0);
-}
-
-/*
- * Utilities for printing HOB information
- */
-
-static void print_guid(const void *base)
-{
- uint32_t big;
- uint16_t mid[2];
-
- const uint8_t *id = base;
- big = read32(id + 0);
- mid[0] = read16(id + 4);
- mid[1] = read16(id + 6);
-
- printk(BIOS_DEBUG, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x",
- big, mid[0], mid[1],
- id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]);
-}
-
-static void print_resource_descriptor(const void *base)
-{
- const struct hob_resource *res;
-
- res = hob_header_to_resource(base);
-
- printk(BIOS_DEBUG, "Resource %s, attribute %x\n",
- resource_name(res->type), res->attribute_type);
- printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length);
- if (!uuid_compare(res->owner_guid, empty_uuid)) {
- printk(BIOS_DEBUG, "\tOwner GUID: ");
- print_guid(res->owner_guid);
- printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid));
- }
-}
-
-
-void fsp_print_memory_resource_hobs(const void *hob_list)
-{
- const struct hob_header *hob = hob_list;
-
- for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) {
- if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR)
- print_resource_descriptor(hob);
- }
-}
-
-const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size)
-{
- const uint8_t *hob_uuid;
- const struct hob_header *hob = fsp_get_hob_list();
-
- if (!hob)
- return NULL;
-
- for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) {
-
- if (hob->type != HOB_TYPE_GUID_EXTENSION)
- continue;
-
- hob_uuid = hob_header_to_struct(hob);
- if (uuid_compare(hob_uuid, uuid)) {
- *size = hob->length - (HOB_HEADER_LEN + 16);
- return hob_header_to_extension_hob(hob);
- }
- }
-
- return NULL;
-}
-
-
-const void *fsp_find_nv_storage_data(size_t *size)
-{
- return fsp_find_extension_hob_by_uuid(uuid_fsp_nv_storage, size);
-}
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
deleted file mode 100644
index d49fc42..0000000
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef _FSP2_0_API_H_
-#define _FSP2_0_API_H_
-
-#include <stddef.h>
-#include <memrange.h>
-#include <fsp/info_header.h>
-#include <soc/fsp/FspmUpd.h>
-#include <soc/fsp/FspsUpd.h>
-
-enum fsp_status {
- FSP_SUCCESS = 0x00000000,
- FSP_INVALID_PARAMETER = 0x80000002,
- FSP_UNSUPPORTED = 0x80000003,
- FSP_NOT_READY = 0x80000006,
- FSP_DEVICE_ERROR = 0x80000007,
- FSP_OUT_OF_RESOURCES = 0x80000009,
- FSP_VOLUME_CORRUPTED = 0x8000000a,
- FSP_NOT_FOUND = 0x8000000a,
- FSP_TIMEOUT = 0x80000012,
- FSP_ABORTED = 0x80000015,
- FSP_INCOMPATIBLE_VERSION = 0x80000010,
- FSP_SECURITY_VIOLATION = 0x8000001a,
- FSP_CRC_ERROR = 0x8000001b,
-};
-
-enum fsp_boot_mode {
- FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00,
- FSP_BOOT_WITH_MINIMAL_CONFIGURATION = 0x01,
- FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES = 0x02,
- FSP_BOOT_ON_S4_RESUME = 0x05,
- FSP_BOOT_ON_S3_RESUME = 0x11,
- FSP_BOOT_ON_FLASH_UPDATE = 0x12,
- FSP_BOOT_IN_RECOVERY_MODE = 0x20
-};
-
-enum fsp_notify_phase {
- AFTER_PCI_ENUM = 0x20,
- READY_TO_BOOT = 0x40
-};
-
-
-/* Main FSP stages */
-enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *r);
-enum fsp_status fsp_silicon_init(struct range_entry *r);
-enum fsp_status fsp_notify(enum fsp_notify_phase phase);
-
-/* Callbacks for updating stage-specific parameters */
-void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd);
-void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd);
-
-/*
- * # DOCUMENTATION:
- *
- * This file defines the interface between coreboot and the FSP 2.0 wrapper
- * fsp_memory_init(), fsp_silicon_init(), and fsp_notify() are the main entry
- * points and map 1:1 to the FSP entry points of the same name.
- *
- * ### fsp_memory_init():
- * - hob_list: retuns a pointer to the HOB storage area created by FSP
- * - r: memory range that the binary is allowed to be loaded into
- *
- * This function is responsible for loading and executing the memory
- * initialization code from the FSP-M binary. It expects this binary to reside
- * in cbfs as FSP_M_FILE.
- *
- * The function takes one parameter, which is described below, but does not
- * take in memory parameters as an argument. The memory parameters can be filled
- * in with platform_fsp_memory_init_params_cb(). This is a callback symbol
- * that fsp_memory_init() will call. The platform must provide this symbol.
- *
- * FSP returns information about the memory layout in a series of structures
- * called hand-off-blocks (HOB). The "hob_list" output parameter will point to
- * the start of the HOB list. The fsp reserved region will also be described by
- * one of the HOBs. For more information on parsing these structures, see
- * fsp/util.h
- *
- *
- * ### fsp_silicon_init():
- * - r: memory range that the binary is allowed to be loaded into
- *
- * This function is responsible for loading and executing the silicon
- * initialization code from the FSP-S binary. It expects this binary to reside
- * in cbfs as FSP_S_FILE.
- *
- * Like fsp_memory_init(), it provides a callback to fill in FSP-specific
- * parameters, via platform_fsp_silicon_init_params_cb(). The platform must
- * also provide this symbol.
- *
- *
- * ### fsp_notify():
- * - phase: Which FSP notification phase
- *
- * This function is responsible for loading and executing the notify code from
- * the FSP-S binary. It expects that fsp_silicon_init() has already been called
- * succesfully, and that the FSP-S binary is still loaded into memory.
- */
-
-#endif /* _FSP2_0_API_H_ */
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
deleted file mode 100644
index 468101e..0000000
--- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef _FSP2_0_INFO_HEADER_H_
-#define _FSP2_0_INFO_HEADER_H_
-
-#include <rules.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <types.h>
-
-#define FSP_HDR_OFFSET 0x94
-#define FSP_HDR_LEN 0x48
-#define FSP_HDR_SIGNATURE "FSPH"
-#define FSP_HDR_ATTRIB_FSPT (0b0001 << 28)
-#define FSP_HDR_ATTRIB_FSPM (0b0010 << 28)
-#define FSP_HDR_ATTRIB_FSPS (0b0011 << 28)
-
-struct fsp_header {
- uint32_t fsp_revision;
- size_t image_size;
- uintptr_t image_base;
- uint32_t image_attribute;
- size_t cfg_region_offset;
- size_t cfg_region_size;
- size_t notify_phase_entry_offset;
- size_t memory_init_entry_offset;
- size_t silicon_init_entry_offset;
- char image_id[sizeof(uint64_t) + 1];
- uint8_t revision;
-};
-
-enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);
-void fsp_print_header_info(const struct fsp_header *hdr);
-void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob);
-
-#if ENV_RAMSTAGE
-/*
- * This is a FSP_INFO_HEADER that came from fsps.bin blob. It contains
- * both SiliconInit and Notify APIs. When SiliconInit is loaded the
- * header is saved so that when Notify is called we do not have to start
- * header parsing again.
- */
-extern struct fsp_header fsps_hdr;
-#endif
-
-#endif /* _FSP2_0_INFO_HEADER_H_ */
diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
deleted file mode 100644
index d9d9539..0000000
--- a/src/drivers/intel/fsp2_0/include/fsp/util.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef _FSP2_0_UTIL_H_
-#define _FSP2_0_UTIL_H_
-
-#include <boot/coreboot_tables.h>
-#include <fsp/info_header.h>
-#include <memrange.h>
-
-/*
- * Hand-off-block handling functions that depend on CBMEM, and thus can only
- * be used after cbmem_initialize().
- */
-void fsp_save_hob_list(void *hob_list_ptr);
-const void *fsp_get_hob_list(void);
-const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size);
-const void *fsp_find_nv_storage_data(size_t *size);
-enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
-/*
- * Hand-off-block utilities which do not depend on CBMEM, but need to be passed
- * the HOB list explicitly.
- */
-void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list);
-void fsp_print_memory_resource_hobs(const void *hob_list);
-
-/* Load an FSP binary into CBFS, and fill the associated fsp_header struct */
-enum cb_err fsp_load_binary(struct fsp_header *hdr, const char *name,
- struct range_entry *r);
-/* Load a vbt.bin file for graphics. Returns 0 if a valid VBT is not found. */
-uintptr_t fsp_load_vbt(void);
-
-#endif /* _FSP2_0_UTIL_H_ */
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
deleted file mode 100644
index 8033937..0000000
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <console/console.h>
-#include <fsp/api.h>
-#include <fsp/util.h>
-#include <memrange.h>
-#include <string.h>
-#include <timestamp.h>
-
-typedef asmlinkage enum fsp_status (*fsp_memory_init_fn)
- (void *raminit_upd, void **hob_list);
-
-static enum fsp_status do_fsp_memory_init(void **hob_list_ptr,
- struct fsp_header *hdr)
-{
- enum fsp_status status;
- fsp_memory_init_fn fsp_raminit;
- struct FSPM_UPD fspm_upd, *upd;
-
- post_code(0x34);
-
- upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
-
- if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) {
- printk(BIOS_ERR, "Invalid FSPM signature\n");
- return FSP_INCOMPATIBLE_VERSION;
- }
-
- /* Copy the default values from the UPD area */
- memcpy(&fspm_upd, upd, sizeof(fspm_upd));
-
- /* Give SoC and mainboard a chance to update the UPD */
- platform_fsp_memory_init_params_cb(&fspm_upd);
-
- /* Call FspMemoryInit */
- fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
- printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit);
- printk(BIOS_SPEW, "\t%p: raminit_upd\n", &fspm_upd);
- printk(BIOS_SPEW, "\t%p: hob_list ptr\n", hob_list_ptr);
-
- timestamp_add_now(TS_FSP_MEMORY_INIT_START);
- status = fsp_raminit(&fspm_upd, hob_list_ptr);
- post_code(0x37);
- timestamp_add_now(TS_FSP_MEMORY_INIT_END);
-
- printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
-
- return status;
-}
-
-enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *range)
-{
- struct fsp_header hdr;
-
- /* TODO: do not hardcode CBFS file names */
- if (fsp_load_binary(&hdr, "blobs/fspm.bin", range) != CB_SUCCESS)
- return FSP_NOT_FOUND;
-
- return do_fsp_memory_init(hob_list, &hdr);
-}
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
deleted file mode 100644
index 820bd45..0000000
--- a/src/drivers/intel/fsp2_0/notify.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <arch/cpu.h>
-#include <console/console.h>
-#include <fsp/api.h>
-#include <fsp/util.h>
-#include <string.h>
-
-struct fsp_notify_params {
- enum fsp_notify_phase phase;
-};
-
-typedef asmlinkage enum fsp_status (*fsp_notify_fn)
- (struct fsp_notify_params *);
-
-enum fsp_status fsp_notify(enum fsp_notify_phase phase)
-{
- fsp_notify_fn fspnotify;
- struct fsp_notify_params notify_params = { .phase = phase };
-
- if (!fsps_hdr.silicon_init_entry_offset)
- return FSP_NOT_FOUND;
-
- fspnotify = (void*) (fsps_hdr.image_base +
- fsps_hdr.notify_phase_entry_offset);
-
- printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase);
-
- return fspnotify(¬ify_params);
-}
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
deleted file mode 100644
index 66043c8..0000000
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <arch/cpu.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <fsp/api.h>
-#include <fsp/util.h>
-#include <string.h>
-
-struct fsp_header fsps_hdr;
-
-typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn)
- (void *silicon_upd);
-
-static enum fsp_status do_silicon_init(struct fsp_header *hdr)
-{
- struct FSPS_UPD upd, *supd;
- fsp_silicon_init_fn silicon_init;
- enum fsp_status status;
-
- supd = (struct FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
-
- if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) {
- printk(BIOS_ERR, "Invalid FSPS signature\n");
- return FSP_INCOMPATIBLE_VERSION;
- }
-
- memcpy(&upd, supd, sizeof(upd));
-
- /* Give SoC/mainboard a chance to populate entries */
- platform_fsp_silicon_init_params_cb(&upd);
-
- silicon_init = (void *) (hdr->image_base +
- hdr->silicon_init_entry_offset);
-
- status = silicon_init(&upd);
- printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
- return status;
-}
-
-enum fsp_status fsp_silicon_init(struct range_entry *range)
-{
- /* Load FSP-S and save FSP header. We will need it for Notify */
- /* TODO: do not hardcode CBFS file names */
- if (fsp_load_binary(&fsps_hdr, "blobs/fsps.bin", range) != CB_SUCCESS)
- return FSP_NOT_FOUND;
-
- return do_silicon_init(&fsps_hdr);
-}
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
deleted file mode 100644
index 743bc9a..0000000
--- a/src/drivers/intel/fsp2_0/util.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <arch/io.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <fsp/util.h>
-#include <lib.h>
-#include <memrange.h>
-#include <program_loading.h>
-#include <string.h>
-
-static bool looks_like_fsp_header(const uint8_t *raw_hdr)
-{
- if (memcmp(raw_hdr, FSP_HDR_SIGNATURE, 4)) {
- printk(BIOS_ALERT, "Did not find a valid FSP signature\n");
- return false;
- }
-
- if (read32(raw_hdr + 4) != FSP_HDR_LEN) {
- printk(BIOS_ALERT, "FSP header has invalid length\n");
- return false;
- }
-
- return true;
-}
-
-enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob)
-{
- const uint8_t *raw_hdr = fsp_blob;
-
- if (!looks_like_fsp_header(raw_hdr))
- return CB_ERR;
-
- hdr->revision = read8(raw_hdr + 11);
- hdr->fsp_revision = read32(raw_hdr + 12);
- memcpy(hdr->image_id, raw_hdr + 16, ARRAY_SIZE(hdr->image_id));
- hdr->image_id[ARRAY_SIZE(hdr->image_id) - 1] = '\0';
- hdr->image_size = read32(raw_hdr + 24);
- hdr->image_base = read32(raw_hdr + 28);
- hdr->image_attribute = read32(raw_hdr + 32);
- hdr->cfg_region_offset = read32(raw_hdr + 36);
- hdr->cfg_region_size = read32(raw_hdr + 40);
- hdr->notify_phase_entry_offset = read32(raw_hdr + 56);
- hdr->memory_init_entry_offset = read32(raw_hdr + 60);
- hdr->silicon_init_entry_offset = read32(raw_hdr + 68);
-
- return CB_SUCCESS;
-}
-
-void fsp_print_header_info(const struct fsp_header *hdr)
-{
- printk(BIOS_DEBUG, "Revision %u, image ID: %s, base 0x%lx + 0x%zx\n",
- hdr->revision, hdr->image_id, hdr->image_base, hdr->image_size);
- printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n",
- hdr->cfg_region_offset, hdr->cfg_region_size);
-
- if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPM) {
- printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n",
- hdr->memory_init_entry_offset);
- }
-
- if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPS) {
- printk(BIOS_DEBUG, "\tSilicon init offset 0x%zx\n",
- hdr->silicon_init_entry_offset);
- printk(BIOS_DEBUG, "\tNotify phase offset 0x%zx\n",
- hdr->notify_phase_entry_offset);
- }
-
-}
-
-/* TODO: this won't work for SoC's that need to XIP certain modules. */
-enum cb_err fsp_load_binary(struct fsp_header *hdr,
- const char *name,
- struct range_entry *range)
-{
- struct cbfsf file_desc;
- struct region_device file_data;
- void *membase;
-
- if (cbfs_boot_locate(&file_desc, name, NULL)) {
- printk(BIOS_ERR, "Could not locate %s in CBFS\n", name);
- return CB_ERR;
- }
-
- cbfs_file_data(&file_data, &file_desc);
-
- /* Map just enough of the file to be able to parse the header. */
- membase = rdev_mmap(&file_data, FSP_HDR_OFFSET, FSP_HDR_LEN);
-
- if (membase == NULL) {
- printk(BIOS_ERR, "Could not mmap() '%s' FSP header.\n", name);
- return CB_ERR;
- }
-
- if (fsp_identify(hdr, membase) != CB_SUCCESS) {
- rdev_munmap(&file_data, membase);
- printk(BIOS_ERR, "%s did not have a valid FSP header\n", name);
- return CB_ERR;
- }
-
- rdev_munmap(&file_data, membase);
-
- fsp_print_header_info(hdr);
-
- /* Check if size specified in the header matches the cbfs file size */
- if (region_device_sz(&file_data) < hdr->image_size) {
- printk(BIOS_ERR, "%s size bigger than cbfs file.\n", name);
- return CB_ERR;
- }
-
- /* Check if the binary load address is within expected range */
- /* TODO: this doesn't check the current running program footprint. */
- if (range_entry_base(range) > hdr->image_base ||
- range_entry_end(range) <= hdr->image_base + hdr->image_size) {
- printk(BIOS_ERR, "%s is outside of allowed range\n", name);
- return CB_ERR;
- }
-
- /* Load binary into memory. */
- if (rdev_readat(&file_data, (void *)hdr->image_base, 0, hdr->image_size) < 0)
- return CB_ERR;
-
- /* Signal that FSP component has been loaded. */
- prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL);
-
- return CB_SUCCESS;
-}
diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig
index 795ad93..6076023 100644
--- a/src/vendorcode/intel/Kconfig
+++ b/src/vendorcode/intel/Kconfig
@@ -23,3 +23,7 @@ config FSP_VENDORCODE_HEADER_PATH
config UEFI_2_4_BINDING
def_bool n
+
+source "src/vendorcode/intel/fsp/fsp1_0/common/Kconfig"
+source "src/vendorcode/intel/fsp/fsp1_1/common/Kconfig"
+source "src/vendorcode/intel/fsp/fsp2_0/common/Kconfig"
diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc
index cf06e36..9d1004b 100644
--- a/src/vendorcode/intel/Makefile.inc
+++ b/src/vendorcode/intel/Makefile.inc
@@ -33,3 +33,7 @@ ifeq ($(CONFIG_UEFI_2_4_BINDING),y)
CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
endif
+
+subdir += fsp/fsp1_0/common
+subdir += fsp/fsp1_1/common
+subdir += fsp/fsp2_0/common
diff --git a/src/vendorcode/intel/fsp/fsp1_0/common/Kconfig b/src/vendorcode/intel/fsp/fsp1_0/common/Kconfig
new file mode 100644
index 0000000..6aa8949
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_0/common/Kconfig
@@ -0,0 +1,127 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if PLATFORM_USES_FSP1_0
+
+comment "Intel FSP"
+
+config HAVE_FSP_BIN
+ bool "Use Intel Firmware Support Package"
+ help
+ Select this option to add an Intel FSP binary to
+ the resulting coreboot image.
+
+ Note: Without this binary, coreboot builds relying on the FSP
+ will not boot
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xfef00000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x4000
+
+if HAVE_FSP_BIN
+
+config FSP_FILE
+ string "Intel FSP binary path and filename"
+ help
+ The path and filename of the Intel FSP binary for this platform.
+
+endif #HAVE_FSP_BIN
+
+config FSP_LOC
+ hex "Intel FSP Binary location in CBFS"
+ help
+ The location in CBFS that the FSP is located. This must match the
+ value that is set in the FSP binary. If the FSP needs to be moved,
+ rebase the FSP with Intel's BCT (tool).
+
+config ENABLE_FSP_FAST_BOOT
+ bool "Enable Fast Boot"
+ select ENABLE_MRC_CACHE
+ default n
+ help
+ Enabling this feature will force the MRC data to be cached in NV
+ storage to be used for speeding up boot time on future reboots
+ and/or power cycles.
+
+config ENABLE_MRC_CACHE
+ bool
+ default y if HAVE_ACPI_RESUME
+ default n
+ help
+ Enabling this feature will cause MRC data to be cached in NV storage.
+ This can either be used for fast boot, or just because the FSP wants
+ it to be saved.
+
+config MRC_CACHE_FMAP
+ bool "Use MRC Cache in FMAP"
+ depends on ENABLE_MRC_CACHE
+ default n
+ help
+ Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
+ You must define a region in your FMAP named "RW_MRC_CACHE".
+
+config MRC_CACHE_SIZE
+ hex "Fast Boot Data Cache Size"
+ default 0x10000
+ depends on ENABLE_MRC_CACHE
+ depends on !MRC_CACHE_FMAP
+ help
+ This is the amount of space in NV storage that is reserved for the
+ fast boot data cache storage.
+
+ WARNING: Because this area will be erased and re-written, the size
+ should be a full sector of the flash ROM chip and nothing else should
+ be included in CBFS in any sector that the fast boot cache data is in.
+
+config VIRTUAL_ROM_SIZE
+ hex "Virtual ROM Size"
+ default ROM_SIZE
+ depends on ENABLE_MRC_CACHE
+ help
+ This is used to calculate the offset of the MRC data cache in NV
+ Storage for fast boot. If in doubt, leave this set to the default
+ which sets the virtual size equal to the ROM size.
+
+ Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are
+ loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When
+ the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
+ size is 16 MB.
+
+config CACHE_ROM_SIZE_OVERRIDE
+ hex "Cache ROM Size"
+ default CBFS_SIZE
+ help
+ This is the size of the cachable area that is passed into the FSP in
+ the early initialization. Typically this should be the size of the CBFS
+ area, but the size must be a power of 2 whereas the CBFS size does not
+ have this limitation.
+
+config USE_GENERIC_FSP_CAR_INC
+ bool
+ default n
+ help
+ The chipset can select this to use a generic cache_as_ram.inc file
+ that should be good for all FSP based platforms.
+
+config FSP_USES_UPD
+ bool
+ default n
+ help
+ If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
+endif #PLATFORM_USES_FSP1_0
diff --git a/src/vendorcode/intel/fsp/fsp1_0/common/Makefile.inc b/src/vendorcode/intel/fsp/fsp1_0/common/Makefile.inc
new file mode 100644
index 0000000..4ff1068
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_0/common/Makefile.inc
@@ -0,0 +1,49 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP1_0),y)
+
+ramstage-y += fsp_util.c hob.c
+romstage-y += fsp_util.c hob.c
+
+ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
+romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
+
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
+
+cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
+
+ifeq ($(CONFIG_HAVE_FSP_BIN),y)
+cbfs-files-y += fsp.bin
+fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
+fsp.bin-position := $(CONFIG_FSP_LOC)
+fsp.bin-type := fsp
+endif
+
+ifeq ($(CONFIG_ENABLE_MRC_CACHE),y)
+ifneq ($(CONFIG_MRC_CACHE_FMAP),y)
+$(obj)/mrc.cache:
+ dd if=/dev/zero count=1 \
+ bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
+ tr '\000' '\377' > $@
+
+cbfs-files-y += mrc.cache
+mrc.cache-file := $(obj)/mrc.cache
+mrc.cache-align := 0x10000
+mrc.cache-type := mrc_cache
+endif
+endif
+
+endif
diff --git a/src/vendorcode/intel/fsp/fsp1_0/common/cache_as_ram.inc b/src/vendorcode/intel/fsp/fsp1_0/common/cache_as_ram.inc
new file mode 100644
index 0000000..e79c3c1
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_0/common/cache_as_ram.inc
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+#include <cbmem.h>
+
+ cmp $0, %eax
+ je cache_as_ram
+ mov $0xa0, %eax
+ jmp .Lhlt
+
+cache_as_ram:
+ post_code(0x20)
+
+ /*
+ * Find the FSP binary in cbfs.
+ * Make a fake stack that has the return value back to this code.
+ */
+ lea fake_fsp_stack, %esp
+ jmp find_fsp
+find_fsp_ret:
+ /* Save the FSP location */
+ mov %eax, %ebp
+ cmp $CONFIG_FSP_LOC, %eax
+ jae find_fsp_ok
+ mov $0xb0, %eax
+ jmp .Lhlt
+
+find_fsp_ok:
+ post_code(POST_FSP_TEMP_RAM_INIT)
+
+ /* Calculate entry into FSP */
+ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
+ add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */
+
+ /*
+ * Pass early init variables on a fake stack (no memory yet)
+ * as well as the return location
+ */
+ lea CAR_init_stack, %esp
+
+ /* call FSP binary to setup temporary stack */
+ jmp *%eax
+
+CAR_init_done:
+ addl $4, %esp
+ cmp $0, %eax
+ je car_init_ok
+ add $0xc0, %eax
+ jmp .Lhlt
+
+car_init_ok:
+
+ /* Save FSP_INFO_HEADER location in ebx */
+ mov %ebp, %ebx
+
+ /*
+ * set up bootloader stack
+ * ecx: stack base
+ * edx: stack top
+ */
+ mov %edx, %esp
+ movl %esp, %ebp
+
+ /* Clear the cbmem CAR memory region. */
+ movl %ecx, %edi
+ movl %edx, %ecx
+ sub %edi, %ecx
+ shr $2, %ecx
+ xorl %eax, %eax
+ rep stosl
+
+before_romstage:
+ post_code(0x23)
+
+ /* Call romstage.c main function. */
+ pushl %ebx /* main takes FSP_INFO_HEADER as its argument */
+ call main /* does not return */
+ movb $0xB8, %ah
+ jmp .Lhlt
+
+.Lhlt:
+#if IS_ENABLED(CONFIG_POST_IO)
+ outb %al, $CONFIG_POST_IO_PORT
+#endif
+ hlt
+ jmp .Lhlt
+
+/*
+ * esp is set to this location so that the call into and return from the FSP
+ * in find_fsp will work.
+ */
+ .align 4
+fake_fsp_stack:
+ .long find_fsp_ret
+
+CAR_init_params:
+ .long dummy_microcode
+ .long 0
+ .long 0xFFFFFFFF - CACHE_ROM_SIZE + 1 /* Firmware Location */
+ .long CACHE_ROM_SIZE /* Total Firmware Length */
+
+CAR_init_stack:
+ .long CAR_init_done
+ .long CAR_init_params
+
+dummy_microcode:
+ .long 0
diff --git a/src/vendorcode/intel/fsp/fsp1_0/common/fastboot_cache.c b/src/vendorcode/intel/fsp/fsp1_0/common/fastboot_cache.c
new file mode 100644
index 0000000..68150f9
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_0/common/fastboot_cache.c
@@ -0,0 +1,257 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <bootstate.h>
+#include <console/console.h>
+#include <cbfs.h>
+#include <fmap.h>
+#include <ip_checksum.h>
+#include <device/device.h>
+#include <cbmem.h>
+#include <spi-generic.h>
+#include <spi_flash.h>
+#include <lib.h> // hexdump
+#include "fsp_util.h"
+
+/* convert a pointer to flash area into the offset inside the flash */
+static inline u32 to_flash_offset(void *p) {
+ return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE);
+}
+
+static struct mrc_data_container *next_mrc_block(
+ struct mrc_data_container *mrc_cache)
+{
+ /* MRC data blocks are aligned within the region */
+ u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size;
+ if (mrc_size & (MRC_DATA_ALIGN - 1UL)) {
+ mrc_size &= ~(MRC_DATA_ALIGN - 1UL);
+ mrc_size += MRC_DATA_ALIGN;
+ }
+
+ u8 *region_ptr = (u8*)mrc_cache;
+ region_ptr += mrc_size;
+ return (struct mrc_data_container *)region_ptr;
+}
+
+static int is_mrc_cache(struct mrc_data_container *mrc_cache)
+{
+ return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE);
+}
+
+static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
+{
+ size_t region_size;
+
+ if (IS_ENABLED(CONFIG_MRC_CACHE_FMAP)) {
+ struct region_device rdev;
+ if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) {
+ *mrc_region_ptr = rdev_mmap_full(&rdev);
+ return region_device_sz(&rdev);
+ }
+ *mrc_region_ptr = NULL;
+ return 0;
+ } else {
+ *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache",
+ CBFS_TYPE_MRC_CACHE,
+ ®ion_size);
+
+ return region_size;
+ }
+}
+
+/*
+ * Find the largest index block in the MRC cache. Return NULL if none is
+ * found.
+ */
+static struct mrc_data_container *find_current_mrc_cache_local
+ (struct mrc_data_container *mrc_cache, u32 region_size)
+{
+ u32 region_end;
+ u32 entry_id = 0;
+ struct mrc_data_container *mrc_next = mrc_cache;
+
+ region_end = (u32) mrc_cache + region_size;
+
+ /* Search for the last filled entry in the region */
+ while (is_mrc_cache(mrc_next)) {
+ entry_id++;
+ mrc_cache = mrc_next;
+ mrc_next = next_mrc_block(mrc_next);
+ if ((u32)mrc_next >= region_end) {
+ /* Stay in the MRC data region */
+ break;
+ }
+ }
+
+ if (entry_id == 0) {
+ printk(BIOS_ERR, "%s: No valid fast boot cache found.\n", __func__);
+ return NULL;
+ }
+
+ /* Verify checksum */
+ if (mrc_cache->mrc_checksum !=
+ compute_ip_checksum(mrc_cache->mrc_data,
+ mrc_cache->mrc_data_size)) {
+ printk(BIOS_ERR, "%s: fast boot cache checksum mismatch\n", __func__);
+ return NULL;
+ }
+
+ printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__,
+ entry_id - 1);
+
+ return mrc_cache;
+}
+
+/* SPI code needs malloc/free.
+ * Also unknown if writing flash from XIP-flash code is a good idea
+ */
+#if !defined(__PRE_RAM__)
+/* find the first empty block in the MRC cache area.
+ * If there's none, return NULL.
+ *
+ * @mrc_cache_base - base address of the MRC cache area
+ * @mrc_cache - current entry (for which we need to find next)
+ * @region_size - total size of the MRC cache area
+ */
+static struct mrc_data_container *find_next_mrc_cache
+ (struct mrc_data_container *mrc_cache_base,
+ struct mrc_data_container *mrc_cache,
+ u32 region_size)
+{
+ u32 region_end = (u32) mrc_cache_base + region_size;
+ u32 mrc_data_size = mrc_cache->mrc_data_size;
+
+ mrc_cache = next_mrc_block(mrc_cache);
+ if (((u32)mrc_cache + mrc_data_size) >= region_end) {
+ /* Crossed the boundary */
+ mrc_cache = NULL;
+ printk(BIOS_DEBUG, "%s: no available entries found\n",
+ __func__);
+ } else {
+ printk(BIOS_DEBUG,
+ "%s: picked next entry from cache block at %p\n",
+ __func__, mrc_cache);
+ }
+
+ return mrc_cache;
+}
+
+void update_mrc_cache(void *unused)
+{
+ printk(BIOS_DEBUG, "Updating fast boot cache data.\n");
+ struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA);
+ struct mrc_data_container *cache, *cache_base;
+ u32 cache_size;
+
+ if (!current) {
+ printk(BIOS_ERR, "No fast boot cache in cbmem. Can't update flash.\n");
+ return;
+ }
+ if (current->mrc_data_size == -1) {
+ printk(BIOS_ERR, "Fast boot cache data in cbmem invalid.\n");
+ return;
+ }
+
+ cache_size = get_mrc_cache_region(&cache_base);
+ if (cache_base == NULL) {
+ printk(BIOS_ERR, "%s: could not find fast boot cache area\n",
+ __func__);
+ return;
+ }
+
+ /*
+ * we need to:
+ * 0. compare MRC data to last mrc-cache block (exit if same)
+ */
+ cache = find_current_mrc_cache_local(cache_base, cache_size);
+
+ if (cache && (cache->mrc_data_size == current->mrc_data_size) &&
+ (memcmp(cache, current, cache->mrc_data_size) == 0)) {
+ printk(BIOS_DEBUG,
+ "MRC data in flash is up to date. No update.\n");
+ return;
+ }
+
+ /* 1. use spi_flash_probe() to find the flash, then... */
+ spi_init();
+ struct spi_flash *flash = spi_flash_probe(0, 0);
+ if (!flash) {
+ printk(BIOS_DEBUG, "Could not find SPI device\n");
+ return;
+ }
+
+ /* 2. look up the first unused block */
+ if (cache)
+ cache = find_next_mrc_cache(cache_base, cache, cache_size);
+
+ /*
+ * 3. if no such place exists, erase entire mrc-cache range & use
+ * block 0. First time around the erase is not needed, but this is a
+ * small overhead for simpler code.
+ */
+ if (!cache) {
+ printk(BIOS_DEBUG,
+ "Need to erase the MRC cache region of %d bytes at %p\n",
+ cache_size, cache_base);
+
+ flash->erase(flash, to_flash_offset(cache_base), cache_size);
+
+ /* we will start at the beginning again */
+ cache = cache_base;
+ }
+ /* 4. write mrc data with flash->write() */
+ printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n",
+ cache);
+ flash->write(flash, to_flash_offset(cache),
+ current->mrc_data_size + sizeof(*current), current);
+}
+
+#endif /* !defined(__PRE_RAM__) */
+
+void * find_and_set_fastboot_cache(void)
+{
+ struct mrc_data_container *mrc_cache = NULL;
+ if (((mrc_cache = find_current_mrc_cache()) == NULL) ||
+ (mrc_cache->mrc_data_size == -1UL)) {
+ printk(BIOS_DEBUG, "FSP MRC cache not present.\n");
+ return NULL;
+ }
+ printk(BIOS_DEBUG, "FSP MRC cache present at %x.\n", (u32)mrc_cache);
+ printk(BIOS_SPEW, "Saved MRC data:\n");
+ hexdump32(BIOS_SPEW, (void *)mrc_cache->mrc_data, (mrc_cache->mrc_data_size) / 4);
+ return (void *) mrc_cache->mrc_data;
+}
+
+struct mrc_data_container *find_current_mrc_cache(void)
+{
+ struct mrc_data_container *cache_base;
+ u32 cache_size;
+
+ cache_size = get_mrc_cache_region(&cache_base);
+ if (cache_base == NULL) {
+ printk(BIOS_ERR, "%s: could not find fast boot cache area\n",
+ __func__);
+ return NULL;
+ }
+
+ /*
+ * we need to:
+ * 0. compare MRC data to last mrc-cache block (exit if same)
+ */
+ return find_current_mrc_cache_local(cache_base, cache_size);
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_0/common/fsp_util.c b/src/vendorcode/intel/fsp/fsp1_0/common/fsp_util.c
new file mode 100644
index 0000000..a3fef2d
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_0/common/fsp_util.c
@@ -0,0 +1,348 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <bootstate.h>
+#include <cbmem.h>
+#include "fsp_util.h"
+#include <lib.h> // hexdump
+#include <ip_checksum.h>
+#include <timestamp.h>
+
+#ifndef __PRE_RAM__
+/* Globals pointers for FSP structures */
+void *FspHobListPtr = NULL;
+FSP_INFO_HEADER *fsp_header_ptr = NULL;
+
+void FspNotify (u32 Phase)
+{
+ FSP_NOTFY_PHASE NotifyPhaseProc;
+ NOTIFY_PHASE_PARAMS NotifyPhaseParams;
+ EFI_STATUS Status;
+
+ if (fsp_header_ptr == NULL) {
+ fsp_header_ptr = (void *)find_fsp();
+ if ((u32)fsp_header_ptr < 0xff) {
+ post_code(0x4F); /* output something in case there is no serial */
+ die("Can't find the FSP!\n");
+ }
+ }
+
+ /* call FSP PEI to Notify PostPciEnumeration */
+ NotifyPhaseProc = (FSP_NOTFY_PHASE)(fsp_header_ptr->ImageBase +
+ fsp_header_ptr->NotifyPhaseEntry);
+ NotifyPhaseParams.Phase = Phase;
+
+ timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ?
+ TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE);
+
+ Status = NotifyPhaseProc (&NotifyPhaseParams);
+
+ timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ?
+ TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE);
+
+ if (Status != 0)
+ printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status);
+}
+#endif /* #ifndef __PRE_RAM__ */
+
+#ifdef __PRE_RAM__
+
+/*
+ * Call the FSP to do memory init. The FSP doesn't return to this function.
+ * The FSP returns to the romstage_main_continue().
+ */
+void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
+{
+ FSP_FSP_INIT FspInitApi;
+ FSP_INIT_PARAMS FspInitParams;
+ FSP_INIT_RT_BUFFER FspRtBuffer;
+#if IS_ENABLED(CONFIG_FSP_USES_UPD)
+ UPD_DATA_REGION fsp_upd_data;
+#endif
+
+ memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));
+ FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP;
+ FspInitParams.NvsBufferPtr = NULL;
+
+#if IS_ENABLED(CONFIG_FSP_USES_UPD)
+ FspRtBuffer.Common.UpdDataRgnPtr = &fsp_upd_data;
+#endif
+ FspInitParams.RtBufferPtr = (FSP_INIT_RT_BUFFER *)&FspRtBuffer;
+ FspInitParams.ContinuationFunc = (CONTINUATION_PROC)ChipsetFspReturnPoint;
+ FspInitApi = (FSP_FSP_INIT)(fsp_ptr->ImageBase + fsp_ptr->FspInitEntry);
+
+ /* Call the chipset code to fill in the chipset specific structures */
+ chipset_fsp_early_init(&FspInitParams, fsp_ptr);
+
+ /* Call back to romstage for board specific changes */
+ romstage_fsp_rt_buffer_callback(&FspRtBuffer);
+
+ post_code(POST_FSP_MEMORY_INIT);
+ FspInitApi(&FspInitParams);
+
+ /* Should never return. Control will continue from ContinuationFunc */
+ die("Uh Oh! FspInitApi returned");
+}
+#endif /* __PRE_RAM__ */
+
+volatile u8 * find_fsp ()
+{
+
+#ifdef __PRE_RAM__
+ volatile register u8 *fsp_ptr asm ("eax");
+
+ /* Entry point for CAR assembly routine */
+ __asm__ __volatile__ (
+ ".global find_fsp\n\t"
+ "find_fsp:\n\t"
+ );
+#else
+ volatile u8 *fsp_ptr;
+#endif /* __PRE_RAM__ */
+
+ /* The FSP is stored in CBFS */
+ fsp_ptr = (u8 *) CONFIG_FSP_LOC;
+
+ /* Check the FV signature, _FVH */
+ if (((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->Signature == 0x4856465F) {
+ /* Go to the end of the FV header and align the address. */
+ fsp_ptr += ((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->ExtHeaderOffset;
+ fsp_ptr += ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)fsp_ptr)->ExtHeaderSize;
+ fsp_ptr = (u8 *)(((u32)fsp_ptr + 7) & 0xFFFFFFF8);
+ } else {
+ fsp_ptr = (u8*)ERROR_NO_FV_SIG;
+ }
+
+ /* Check the FFS GUID */
+ if (((u32)fsp_ptr > 0xff) &&
+ (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[0] == 0x912740BE) &&
+ (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[1] == 0x47342284) &&
+ (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[2] == 0xB08471B9) &&
+ (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[3] == 0x0C3F3527)) {
+ /* Add the FFS Header size to the base to find the Raw section Header */
+ fsp_ptr += sizeof(EFI_FFS_FILE_HEADER);
+ } else {
+ fsp_ptr = (u8 *)ERROR_NO_FFS_GUID;
+ }
+
+ if (((u32)fsp_ptr > 0xff) &&
+ ((EFI_RAW_SECTION *)fsp_ptr)->Type == EFI_SECTION_RAW) {
+ /* Add the Raw Header size to the base to find the FSP INFO Header */
+ fsp_ptr += sizeof(EFI_RAW_SECTION);
+ } else {
+ fsp_ptr = (u8 *)ERROR_NO_INFO_HEADER;
+ }
+
+ /* Verify that the FSP is set to the base address we're expecting.*/
+ if (((u32)fsp_ptr > 0xff) &&
+ (*(u32*)(fsp_ptr + FSP_IMAGE_BASE_LOC) != CONFIG_FSP_LOC)) {
+ fsp_ptr = (u8 *)ERROR_IMAGEBASE_MISMATCH;
+ }
+
+ /* Verify the FSP Signature */
+ if (((u32)fsp_ptr > 0xff) &&
+ (*(u32*)(fsp_ptr + FSP_IMAGE_SIG_LOC) != FSP_SIG)){
+ fsp_ptr = (u8 *)ERROR_INFO_HEAD_SIG_MISMATCH;
+ }
+
+ /* Verify the FSP ID */
+ if (((u32)fsp_ptr > 0xff) &&
+ ((*(u32 *)(fsp_ptr + FSP_IMAGE_ID_LOC) != FSP_IMAGE_ID_DWORD0) ||
+ (*(u32 *)(fsp_ptr + (FSP_IMAGE_ID_LOC + 4)) != FSP_IMAGE_ID_DWORD1))) {
+ fsp_ptr = (u8 *)ERROR_FSP_SIG_MISMATCH;
+ }
+
+ return (fsp_ptr);
+}
+
+/** finds the saved temporary memory information in the FSP HOB list
+ *
+ * @param hob_list_ptr pointer to the start of the hob list
+ * @return pointer to saved CAR MEM or NULL if not found.
+ */
+void * find_saved_temp_mem(void *hob_list_ptr)
+{
+ EFI_GUID temp_hob_guid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID;
+ EFI_HOB_GUID_TYPE *saved_mem_hob =
+ (EFI_HOB_GUID_TYPE *) find_hob_by_guid(
+ hob_list_ptr, &temp_hob_guid);
+
+ if (saved_mem_hob == NULL)
+ return NULL;
+
+ return (void *) ((char *) saved_mem_hob + sizeof(EFI_HOB_GUID_TYPE));
+}
+
+#ifndef FSP_RESERVE_MEMORY_SIZE
+/** @brief locates the HOB containing the location of the fsp reserved mem area
+ *
+ * @param hob_list_ptr pointer to the start of the hob list
+ * @return pointer to the start of the FSP reserved memory or NULL if not found.
+ */
+void * find_fsp_reserved_mem(void *hob_list_ptr)
+{
+ EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
+ EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem =
+ (EFI_HOB_RESOURCE_DESCRIPTOR *) find_hob_by_guid(
+ hob_list_ptr, &fsp_reserved_guid);
+
+ if (fsp_reserved_mem == NULL)
+ return NULL;
+
+ return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart);
+}
+#endif /* FSP_RESERVE_MEMORY_SIZE */
+
+#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */
+
+void print_fsp_info(void) {
+
+ if (fsp_header_ptr == NULL)
+ fsp_header_ptr = (void *)find_fsp();
+
+ if ((u32)fsp_header_ptr < 0xff) {
+ post_code(0x4F); /* post code in case there is no serial */
+ die("Can't find the FSP!\n");
+ }
+
+ if (FspHobListPtr == NULL) {
+ FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));
+ }
+
+ printk(BIOS_SPEW,"fsp_header_ptr: %p\n", fsp_header_ptr);
+ printk(BIOS_INFO,"FSP Header Version: %d\n", fsp_header_ptr->HeaderRevision);
+ printk(BIOS_INFO,"FSP Revision: %d.%d\n",
+ (u8)((fsp_header_ptr->ImageRevision >> 8) & 0xff),
+ (u8)(fsp_header_ptr->ImageRevision & 0xff));
+}
+
+
+#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
+/**
+ * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM
+ */
+int save_mrc_data(void *hob_start)
+{
+ u32 *mrc_hob;
+ u32 *mrc_hob_data;
+ u32 mrc_hob_size;
+ struct mrc_data_container *mrc_data;
+ int output_len;
+ const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+
+ mrc_hob = GetNextGuidHob(&mrc_guid, hob_start);
+ if (mrc_hob == NULL){
+ printk(BIOS_DEBUG, "Memory Configure Data Hob is not present\n");
+ return(0);
+ }
+
+ mrc_hob_data = GET_GUID_HOB_DATA (mrc_hob);
+ mrc_hob_size = (u32) GET_HOB_LENGTH(mrc_hob);
+
+ printk(BIOS_DEBUG, "Memory Configure Data Hob at %p (size = 0x%x).\n",
+ (void *)mrc_hob_data, mrc_hob_size);
+
+ output_len = ALIGN(mrc_hob_size, 16);
+
+ /* Save the MRC S3/fast boot/ADR restore data to cbmem */
+ mrc_data = cbmem_add (CBMEM_ID_MRCDATA,
+ output_len + sizeof(struct mrc_data_container));
+
+ /* Just return if there was a problem with getting CBMEM */
+ if (mrc_data == NULL) {
+ printk(BIOS_WARNING, "CBMEM was not available to save the fast boot cache data.\n");
+ return 0;
+ }
+
+ printk(BIOS_DEBUG, "Copy FSP MRC DATA to HOB (source addr %p, dest addr %p, %u bytes)\n",
+ (void *)mrc_hob_data, mrc_data, output_len);
+
+ mrc_data->mrc_signature = MRC_DATA_SIGNATURE;
+ mrc_data->mrc_data_size = output_len;
+ mrc_data->reserved = 0;
+ memcpy(mrc_data->mrc_data, (const void *)mrc_hob_data, mrc_hob_size);
+
+ /* Zero the unused space in aligned buffer. */
+ if (output_len > mrc_hob_size)
+ memset((mrc_data->mrc_data + mrc_hob_size), 0,
+ output_len - mrc_hob_size);
+
+ mrc_data->mrc_checksum = compute_ip_checksum(mrc_data->mrc_data,
+ mrc_data->mrc_data_size);
+
+ printk(BIOS_SPEW, "Fast boot data (includes align and checksum):\n");
+ hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4);
+ return (1);
+}
+#endif /* CONFIG_ENABLE_MRC_CACHE */
+
+static void find_fsp_hob_update_mrc(void *unused)
+{
+ /* Set the global HOB list pointer */
+ FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));
+
+ if (!FspHobListPtr){
+ printk(BIOS_ERR, "ERROR: Could not find FSP HOB pointer in CBFS!\n");
+ } else {
+ /* 0x0000: Print all types */
+ print_hob_type_structure(0x000, FspHobListPtr);
+
+ #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
+ if(save_mrc_data(FspHobListPtr))
+ update_mrc_cache(NULL);
+ else
+ printk(BIOS_DEBUG,"Not updating MRC data in flash.\n");
+ #endif
+ }
+}
+
+/** @brief Notify FSP for PostPciEnumeration
+ *
+ * @param unused
+ */
+static void fsp_after_pci_enum(void *unused)
+{
+ /* This call needs to be done before resource allocation. */
+ printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
+ post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
+ FspNotify(EnumInitPhaseAfterPciEnumeration);
+ printk(BIOS_DEBUG,
+ "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
+}
+
+/** @brief Notify FSP for ReadyToBoot
+ *
+ * @param unused
+ */
+static void fsp_finalize(void *unused)
+{
+ printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n");
+ print_fsp_info();
+ post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
+ FspNotify(EnumInitPhaseReadyToBoot);
+ printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n");
+}
+
+/* Set up for the ramstage FSP calls */
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL);
+
+/* Update the MRC/fast boot cache as part of the late table writing stage */
+BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
+ find_fsp_hob_update_mrc, NULL);
+#endif /* #ifndef __PRE_RAM__ */
diff --git a/src/vendorcode/intel/fsp/fsp1_0/common/fsp_util.h b/src/vendorcode/intel/fsp/fsp1_0/common/fsp_util.h
new file mode 100644
index 0000000..bbdd4de
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_0/common/fsp_util.h
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef FSP_UTIL_H
+#define FSP_UTIL_H
+
+#include <chipset_fsp_util.h>
+#include "fsp_values.h"
+
+#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
+int save_mrc_data(void *hob_start);
+void * find_and_set_fastboot_cache(void);
+#endif
+
+volatile u8 * find_fsp (void);
+void fsp_early_init(FSP_INFO_HEADER *fsp_info);
+void FspNotify(u32 Phase);
+void FspNotifyReturnPoint(EFI_STATUS Status, VOID *HobListPtr);
+void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer);
+void print_fsp_info(void);
+void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams,
+ FSP_INFO_HEADER *fsp_ptr);
+void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr);
+void * find_saved_temp_mem(void *hob_list_ptr);
+void * find_fsp_reserved_mem(void *hob_list_ptr);
+
+/* functions in hob.c */
+void print_hob_mem_attributes(void *Hobptr);
+void print_hob_type_structure(u16 Hobtype, void *Hoblistptr);
+void print_hob_resource_attributes(void *Hobptr);
+void print_guid_type_attributes(void *Hobptr);
+const char * get_hob_type_string(void *Hobptr);
+void * find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1);
+uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2);
+void printguid(EFI_GUID *guid);
+
+/* Additional HOB types not included in the FSP:
+ * #define EFI_HOB_TYPE_HANDOFF 0x0001
+ * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
+ * #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
+ * #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
+ * #define EFI_HOB_TYPE_FV 0x0005
+ * #define EFI_HOB_TYPE_CPU 0x0006
+ * #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
+ * #define EFI_HOB_TYPE_CV 0x0008
+ * #define EFI_HOB_TYPE_UNUSED 0xFFFE
+ * #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff
+ */
+#define EFI_HOB_TYPE_HANDOFF 0x0001
+#define EFI_HOB_TYPE_MEMORY_POOL 0x0007
+
+#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
+#define MRC_DATA_ALIGN 0x1000
+#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
+
+struct mrc_data_container {
+ u32 mrc_signature; // "MRCD"
+ u32 mrc_data_size; // Actual total size of this structure
+ u32 mrc_checksum; // IP style checksum
+ u32 reserved; // For header alignment
+ u8 mrc_data[0]; // Variable size, platform/run time dependent.
+} __attribute__ ((packed));
+
+struct mrc_data_container *find_current_mrc_cache(void);
+
+#if !defined(__PRE_RAM__)
+void update_mrc_cache(void *unused);
+#endif
+
+#endif
+
+/* The offset in bytes from the start of the info structure */
+#define FSP_IMAGE_SIG_LOC 0
+#define FSP_IMAGE_ID_LOC 16
+#define FSP_IMAGE_BASE_LOC 28
+
+#define FSP_SIG 0x48505346 /* 'FSPH' */
+
+#define ERROR_NO_FV_SIG 1
+#define ERROR_NO_FFS_GUID 2
+#define ERROR_NO_INFO_HEADER 3
+#define ERROR_IMAGEBASE_MISMATCH 4
+#define ERROR_INFO_HEAD_SIG_MISMATCH 5
+#define ERROR_FSP_SIG_MISMATCH 6
+
+#ifndef __PRE_RAM__
+extern void *FspHobListPtr;
+#endif
+
+#define UPD_DEFAULT_CHECK(member) \
+ if (config->member != UPD_DEFAULT) { \
+ UpdData->member = config->member - 1; \
+ } \
+ printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \
+ config->member ? "(set)" : "(default)");
+
+#define UPD_SPD_CHECK(member) \
+ if (config->member == UPD_SPD_ADDR_DISABLED) { \
+ UpdData->member = 0x00; \
+ } else if (config->member != UPD_SPD_ADDR_DEFAULT) { \
+ UpdData->member = config->member; \
+ } \
+ printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \
+ config->member ? "(set)" : "(default)");
+
+#define UPD_DEVICE_CHECK(devicename, member, statement) \
+ case devicename: \
+ UpdData->member = dev->enabled; \
+ printk(FSP_INFO_LEVEL, statement "%s\n", \
+ UpdData->member?"Enabled":"Disabled"); \
+ break;
+
+
+#ifndef FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID
+#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \
+ { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } };
+#endif
+
+#endif /* FSP_UTIL_H */
diff --git a/src/vendorcode/intel/fsp/fsp1_0/common/fsp_values.h b/src/vendorcode/intel/fsp/fsp1_0/common/fsp_values.h
new file mode 100644
index 0000000..337e751
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_0/common/fsp_values.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef FSP_VALUES_H
+#define FSP_VALUES_H
+
+#ifndef FSP_DEBUG_LEVEL
+# define FSP_DEBUG_LEVEL BIOS_SPEW
+#endif
+
+#ifndef FSP_INFO_LEVEL
+# define FSP_INFO_LEVEL BIOS_DEBUG
+#endif
+
+#define INCREMENT_FOR_DEFAULT(x) (x+1)
+
+#define UPD_DEFAULT 0x00
+#define UPD_DISABLE INCREMENT_FOR_DEFAULT(0)
+#define UPD_ENABLE INCREMENT_FOR_DEFAULT(1)
+#define UPD_USE_DEVICETREE 0xff
+
+#define UPD_SPD_ADDR_DEFAULT UPD_DEFAULT
+#define UPD_SPD_ADDR_DISABLED 0xFF
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp1_0/common/hob.c b/src/vendorcode/intel/fsp/fsp1_0/common/hob.c
new file mode 100644
index 0000000..4aac147
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_0/common/hob.c
@@ -0,0 +1,265 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <lib.h> // hexdump
+#include "fsp_util.h"
+
+
+/** Displays a GUID's address and value
+ *
+ * @param guid pointer to the GUID to display
+ */
+void printguid(EFI_GUID *guid)
+{
+ printk(BIOS_SPEW,"Address: %p Guid: %08lx-%04x-%04x-",
+ guid, (unsigned long)guid->Data1,
+ guid->Data2, guid->Data3);
+ printk(BIOS_SPEW,"%02x%02x%02x%02x%02x%02x%02x%02x\n",
+ guid->Data4[0], guid->Data4[1],
+ guid->Data4[2], guid->Data4[3],
+ guid->Data4[4], guid->Data4[5],
+ guid->Data4[6], guid->Data4[7] );
+}
+
+void print_hob_mem_attributes(void *Hobptr)
+{
+ EFI_HOB_MEMORY_ALLOCATION *HobMemoryPtr = (EFI_HOB_MEMORY_ALLOCATION *)Hobptr;
+ EFI_MEMORY_TYPE Hobmemtype = HobMemoryPtr->AllocDescriptor.MemoryType;
+ u64 Hobmemaddr = HobMemoryPtr->AllocDescriptor.MemoryBaseAddress;
+ u64 Hobmemlength = HobMemoryPtr->AllocDescriptor.MemoryLength;
+ const char * Hobmemtypenames[15];
+
+ Hobmemtypenames[0] = "EfiReservedMemoryType";
+ Hobmemtypenames[1] = "EfiLoaderCode";
+ Hobmemtypenames[2] = "EfiLoaderData";
+ Hobmemtypenames[3] = "EfiBootServicesCode";
+ Hobmemtypenames[4] = "EfiBootServicesData";
+ Hobmemtypenames[5] = "EfiRuntimeServicesCode";
+ Hobmemtypenames[6] = "EfiRuntimeServicesData";
+ Hobmemtypenames[7] = "EfiConventionalMemory";
+ Hobmemtypenames[8] = "EfiUnusableMemory";
+ Hobmemtypenames[9] = "EfiACPIReclaimMemory";
+ Hobmemtypenames[10] = "EfiACPIMemoryNVS";
+ Hobmemtypenames[11] = "EfiMemoryMappedIO";
+ Hobmemtypenames[12] = "EfiMemoryMappedIOPortSpace";
+ Hobmemtypenames[13] = "EfiPalCode";
+ Hobmemtypenames[14] = "EfiMaxMemoryType";
+
+ printk(BIOS_SPEW, " Memory type %s (0x%x)\n",
+ Hobmemtypenames[(u32)Hobmemtype], (u32) Hobmemtype);
+ printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n",
+ (unsigned long)Hobmemaddr, (unsigned long)Hobmemlength);
+}
+
+void print_hob_resource_attributes(void *Hobptr)
+{
+ EFI_HOB_RESOURCE_DESCRIPTOR *HobResourcePtr =
+ (EFI_HOB_RESOURCE_DESCRIPTOR *)Hobptr;
+ u32 Hobrestype = HobResourcePtr->ResourceType;
+ u32 Hobresattr = HobResourcePtr->ResourceAttribute;
+ u64 Hobresaddr = HobResourcePtr->PhysicalStart;
+ u64 Hobreslength = HobResourcePtr->ResourceLength;
+ const char *Hobrestypestr = NULL;
+
+ // HOB Resource Types
+ switch (Hobrestype) {
+ case EFI_RESOURCE_SYSTEM_MEMORY:
+ Hobrestypestr = "EFI_RESOURCE_SYSTEM_MEMORY"; break;
+ case EFI_RESOURCE_MEMORY_MAPPED_IO:
+ Hobrestypestr = "EFI_RESOURCE_MEMORY_MAPPED_IO"; break;
+ case EFI_RESOURCE_IO:
+ Hobrestypestr = "EFI_RESOURCE_IO"; break;
+ case EFI_RESOURCE_FIRMWARE_DEVICE:
+ Hobrestypestr = "EFI_RESOURCE_FIRMWARE_DEVICE"; break;
+ case EFI_RESOURCE_MEMORY_MAPPED_IO_PORT:
+ Hobrestypestr = "EFI_RESOURCE_MEMORY_MAPPED_IO_PORT"; break;
+ case EFI_RESOURCE_MEMORY_RESERVED:
+ Hobrestypestr = "EFI_RESOURCE_MEMORY_RESERVED"; break;
+ case EFI_RESOURCE_IO_RESERVED:
+ Hobrestypestr = "EFI_RESOURCE_IO_RESERVED"; break;
+ case EFI_RESOURCE_MAX_MEMORY_TYPE:
+ Hobrestypestr = "EFI_RESOURCE_MAX_MEMORY_TYPE"; break;
+ default:
+ Hobrestypestr = "EFI_RESOURCE_UNKNOWN"; break;
+ }
+
+ printk(BIOS_SPEW, " Resource %s (0x%0x) has attributes 0x%0x\n",
+ Hobrestypestr, Hobrestype, Hobresattr);
+ printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n",
+ (unsigned long)Hobresaddr, (unsigned long)Hobreslength);
+}
+
+const char * get_hob_type_string(void *Hobptr)
+{
+ EFI_HOB_GENERIC_HEADER *HobHeaderPtr = (EFI_HOB_GENERIC_HEADER *)Hobptr;
+ u16 Hobtype = HobHeaderPtr->HobType;
+ const char *Hobtypestring = NULL;
+
+ switch (Hobtype) {
+ case EFI_HOB_TYPE_HANDOFF:
+ Hobtypestring = "EFI_HOB_TYPE_HANDOFF"; break;
+ case EFI_HOB_TYPE_MEMORY_ALLOCATION:
+ Hobtypestring = "EFI_HOB_TYPE_MEMORY_ALLOCATION"; break;
+ case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
+ Hobtypestring = "EFI_HOB_TYPE_RESOURCE_DESCRIPTOR"; break;
+ case EFI_HOB_TYPE_GUID_EXTENSION:
+ Hobtypestring = "EFI_HOB_TYPE_GUID_EXTENSION"; break;
+ case EFI_HOB_TYPE_MEMORY_POOL:
+ Hobtypestring = "EFI_HOB_TYPE_MEMORY_POOL"; break;
+ case EFI_HOB_TYPE_UNUSED:
+ Hobtypestring = "EFI_HOB_TYPE_UNUSED"; break;
+ case EFI_HOB_TYPE_END_OF_HOB_LIST:
+ Hobtypestring = "EFI_HOB_TYPE_END_OF_HOB_LIST"; break;
+ default:
+ Hobtypestring = "EFI_HOB_TYPE_UNRECOGNIZED"; break;
+ }
+
+ return Hobtypestring;
+}
+
+/** Displays the length, location, and GUID value of a GUID extension
+ *
+ * The EFI_HOB_GUID_TYPE is very basic - it just contains the standard
+ * HOB header containing the HOB type and length, and a GUID for
+ * identification. The rest of the data is undefined and must be known
+ * based on the GUID.
+ *
+ * This displays the entire HOB length, and the location of the start
+ * of the HOB, *NOT* the length of or the start of the data inside the HOB.
+ *
+ * @param Hobptr
+ */
+void print_guid_type_attributes(void *Hobptr)
+{
+ printk(BIOS_SPEW, " at location %p with length0x%0lx\n ",
+ Hobptr, (unsigned long)(((EFI_PEI_HOB_POINTERS *) \
+ Hobptr)->Guid->Header.HobLength));
+ printguid(&(((EFI_HOB_GUID_TYPE *)Hobptr)->Name));
+
+}
+
+/* Print out a structure of all the HOBs
+ * that match a certain type:
+ * Print all types (0x0000)
+ * EFI_HOB_TYPE_HANDOFF (0x0001)
+ * EFI_HOB_TYPE_MEMORY_ALLOCATION (0x0002)
+ * EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (0x0003)
+ * EFI_HOB_TYPE_GUID_EXTENSION (0x0004)
+ * EFI_HOB_TYPE_MEMORY_POOL (0x0007)
+ * EFI_HOB_TYPE_UNUSED (0xFFFE)
+ * EFI_HOB_TYPE_END_OF_HOB_LIST (0xFFFF)
+ */
+void print_hob_type_structure(u16 Hobtype, void *Hoblistptr)
+{
+ u32 *Currenthob;
+ u32 *Nexthob = 0;
+ u8 Lasthob = 0;
+ u32 Currenttype;
+ const char *Currenttypestr;
+
+ Currenthob = Hoblistptr;
+
+ /* Print out HOBs of our desired type until
+ * the end of the HOB list
+ */
+ printk(BIOS_DEBUG, "\n=== FSP HOB Data Structure ===\n");
+ printk(BIOS_DEBUG, "FSP Hoblistptr: 0x%0x\n",
+ (u32) Hoblistptr);
+ do {
+ EFI_HOB_GENERIC_HEADER *CurrentHeaderPtr =
+ (EFI_HOB_GENERIC_HEADER *)Currenthob;
+ Currenttype = CurrentHeaderPtr->HobType; /* Get the type of this HOB */
+ Currenttypestr = get_hob_type_string(Currenthob);
+
+ if (Currenttype == Hobtype || Hobtype == 0x0000) {
+ printk(BIOS_DEBUG, "HOB 0x%0x is an %s (type 0x%0x)\n",
+ (u32) Currenthob, Currenttypestr, Currenttype);
+ switch (Currenttype) {
+ case EFI_HOB_TYPE_MEMORY_ALLOCATION:
+ print_hob_mem_attributes(Currenthob); break;
+ case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
+ print_hob_resource_attributes(Currenthob); break;
+ case EFI_HOB_TYPE_GUID_EXTENSION:
+ print_guid_type_attributes(Currenthob); break;
+ }
+ }
+
+ Lasthob = END_OF_HOB_LIST(Currenthob); /* Check for end of HOB list */
+ if (!Lasthob) {
+ Nexthob = GET_NEXT_HOB(Currenthob); /* Get next HOB pointer */
+ Currenthob = Nexthob; // Start on next HOB
+ }
+ } while (!Lasthob);
+ printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n");
+}
+
+
+/** Finds a HOB entry based on type and guid
+ *
+ * @param current_hob pointer to the start of the HOB list
+ * @param guid the GUID of the HOB entry to find
+ * @return pointer to the start of the requested HOB or NULL if not found.
+ */
+void * find_hob_by_guid(void *current_hob, EFI_GUID *guid)
+{
+ do {
+ switch (((EFI_HOB_GENERIC_HEADER *)current_hob)->HobType) {
+
+ case EFI_HOB_TYPE_MEMORY_ALLOCATION:
+ if (guids_are_equal(guid, &(((EFI_HOB_MEMORY_ALLOCATION *) \
+ current_hob)->AllocDescriptor.Name)))
+ return current_hob;
+ break;
+ case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
+ if (guids_are_equal(guid,
+ &(((EFI_HOB_RESOURCE_DESCRIPTOR *) \
+ current_hob)->Owner)))
+ return current_hob;
+ break;
+ case EFI_HOB_TYPE_GUID_EXTENSION:
+ if (guids_are_equal(guid, &(((EFI_HOB_GUID_TYPE *) \
+ current_hob)->Name)))
+ return current_hob;
+ break;
+ }
+
+ if (!END_OF_HOB_LIST(current_hob))
+ current_hob = GET_NEXT_HOB(current_hob); /* Get next HOB pointer */
+ } while (!END_OF_HOB_LIST(current_hob));
+
+ return NULL;
+}
+
+/** Compares a pair of GUIDs to see if they are equal
+ *
+ * GUIDs are 128 bits long, so compare them as pairs of quadwords.
+ *
+ * @param guid1 pointer to the first of the GUIDs to compare
+ * @param guid2 pointer to the second of the GUIDs to compare
+ * @return 1 if the GUIDs were equal, 0 if GUIDs were not equal
+ */
+uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2)
+{
+ uint64_t* guid_1 = (void *) guid1;
+ uint64_t* guid_2 = (void *) guid2;
+
+ if ((*(guid_1) != *(guid_2)) || (*(guid_1 + 1) != *(guid_2 + 1)))
+ return 0;
+
+ return 1;
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/Kconfig b/src/vendorcode/intel/fsp/fsp1_1/common/Kconfig
new file mode 100644
index 0000000..9b2c463
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/Kconfig
@@ -0,0 +1,118 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config PLATFORM_USES_FSP1_1
+ bool
+ select UEFI_2_4_BINDING
+ help
+ Does the code require the Intel Firmware Support Package?
+
+if PLATFORM_USES_FSP1_1
+
+comment "Intel FSP 1.1"
+
+config HAVE_FSP_BIN
+ bool "Should the Intel FSP binary be added to the flash image"
+ help
+ Select this option to add an Intel FSP binary to
+ the resulting coreboot image.
+
+ Note: Without this binary, coreboot builds relying on the FSP
+ will not boot
+
+config CPU_MICROCODE_CBFS_LEN
+ hex "Microcode update region length in bytes"
+ default 0
+ help
+ The length in bytes of the microcode update region.
+
+config CPU_MICROCODE_CBFS_LOC
+ hex "Microcode update base address in CBFS"
+ default 0
+ help
+ The location (base address) in CBFS that contains the microcode update
+ binary.
+
+config FSP_FILE
+ string "Intel FSP binary path and filename"
+ help
+ The path and filename of the Intel FSP binary for this platform.
+
+config FSP_IMAGE_ID_STRING
+ string "8 byte platform string identifying the FSP platform"
+ default "$XXXFSP$"
+ help
+ 8 ASCII character byte signature string that will help match the FSP
+ binary to a supported hardware configuration.
+
+config FSP_LOC
+ hex "Intel FSP Binary location in CBFS"
+ default 0xffee0000
+ help
+ The location in CBFS that the FSP is located. This must match the
+ value that is set in the FSP binary. If the FSP needs to be moved,
+ rebase the FSP with Intel's BCT (tool).
+
+config DISPLAY_FAST_BOOT_DATA
+ bool "Display fast boot data"
+ default n
+
+config DISPLAY_HOBS
+ bool "Display hand-off-blocks (HOBs)"
+ default n
+
+config DISPLAY_VBT
+ bool "Display Video BIOS Table (VBT)"
+ default n
+
+config DISPLAY_FSP_ENTRY_POINTS
+ bool "Display FSP entry points"
+ default n
+
+config DISPLAY_UPD_DATA
+ bool "Display UPD data"
+ default n
+ help
+ Display the user specified product data prior to memory
+ initialization.
+
+config FSP_USES_UPD
+ bool
+ default n
+ help
+ If this FSP uses UPD/VPD data regions, select this in the chipset
+ Kconfig.
+
+config GOP_SUPPORT
+ bool "Enable GOP support"
+ default n
+
+config ROMSTAGE_RAM_STACK_SIZE
+ hex "Size of the romstage RAM stack in bytes"
+ default 0x5000
+
+config USE_GENERIC_FSP_CAR_INC
+ bool
+ default n
+ help
+ The chipset can select this to use a generic cache_as_ram.inc file
+ that should be good for all FSP based platforms.
+
+config VBT_FILE
+ string "GOP Video BIOS table binary path"
+ depends on GOP_SUPPORT
+ default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin"
+
+endif #PLATFORM_USES_FSP1_1
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/Makefile.inc b/src/vendorcode/intel/fsp/fsp1_1/common/Makefile.inc
new file mode 100644
index 0000000..3f214cb
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/Makefile.inc
@@ -0,0 +1,59 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+# Copyright (C) 2015 Intel Corp.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
+
+verstage-y += car.c
+verstage-y += fsp_util.c
+verstage-y += verstage.c
+
+romstage-y += car.c
+romstage-y += fsp_util.c
+romstage-y += hob.c
+romstage-y += raminit.c
+romstage-y += romstage.c
+romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
+romstage-y += stack.c
+romstage-y += stage_cache.c
+
+ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
+ramstage-y += fsp_relocate.c
+ramstage-y += fsp_util.c
+ramstage-y += hob.c
+ramstage-y += ramstage.c
+ramstage-y += stage_cache.c
+ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
+
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
+
+cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
+
+
+# Add the GOP Video BIOS Table to the cbfs image
+cbfs-files-$(CONFIG_GOP_SUPPORT) += vbt.bin
+vbt.bin-file := $(call strip_quotes,$(CONFIG_VBT_FILE))
+vbt.bin-type := optionrom
+
+
+# Add the FSP binary to the cbfs image
+ifeq ($(CONFIG_HAVE_FSP_BIN),y)
+cbfs-files-y += fsp.bin
+fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
+fsp.bin-position := $(CONFIG_FSP_LOC)
+fsp.bin-type := fsp
+endif
+
+endif
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/after_raminit.S b/src/vendorcode/intel/fsp/fsp1_1/common/after_raminit.S
new file mode 100644
index 0000000..122c0bf
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/after_raminit.S
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+/*
+ * This is the common entry point after DRAM has been initialized.
+ */
+ /*
+ * eax: New stack address
+ */
+
+ /* Switch to the stack in RAM */
+ movl %eax, %esp
+
+#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
+
+ /* SOC specific NEM */
+ #include <soc/car_teardown.S>
+
+#else
+.extern fih_car
+
+ post_code(POST_FSP_TEMP_RAM_EXIT)
+
+ /* Calculate TempRamExit entry into FSP */
+ movl fih_car, %ebp
+ mov 0x40(%ebp), %eax
+ add 0x1c(%ebp), %eax
+
+ /* Build the call frame */
+ pushl $0
+
+ /* Call TempRamExit */
+ call *%eax
+ add $4, %esp
+ cmp $0, %eax
+ jz 1f
+ /*
+ * Failures for post code BC - failed in TempRamExit
+ *
+ * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully.
+ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
+ * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
+ * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed.
+ */
+ movb $0xBC, %ah
+ jmp .Lhlt
+1:
+#endif
+ /* Display the MTRRs */
+ call soc_display_mtrrs
+
+ /*
+ * The stack contents are initialized in src/soc/intel/common/stack.c
+ * to be the following:
+ *
+ * *
+ * *
+ * *
+ * +36: MTRR mask 1 63:32
+ * +32: MTRR mask 1 31:0
+ * +28: MTRR base 1 63:32
+ * +24: MTRR base 1 31:0
+ * +20: MTRR mask 0 63:32
+ * +16: MTRR mask 0 31:0
+ * +12: MTRR base 0 63:32
+ * +8: MTRR base 0 31:0
+ * +4: Number of MTRRs to setup (described above)
+ * +0: Number of variable MTRRs to clear
+ */
+
+#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
+ push %esp
+ call soc_set_mtrrs
+
+ /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */
+ movl %eax, %esp
+#else
+ /* Clear all of the variable MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+ clr %eax
+ clr %edx
+
+1:
+ testl %ebx, %ebx
+ jz 1f
+ wrmsr /* Write MTRR base. */
+ inc %ecx
+ wrmsr /* Write MTRR mask. */
+ inc %ecx
+ dec %ebx
+ jmp 1b
+
+1:
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+2:
+ testl %ebx, %ebx
+ jz 2f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
+ wrmsr
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
+ wrmsr
+ inc %ecx
+
+ dec %ebx
+ jmp 2b
+2:
+#endif /* CONFIG_SOC_SETS_MTRRS */
+
+ post_code(0x39)
+
+ /* And enable cache again after setting MTRRs. */
+ movl %cr0, %eax
+ andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+ movl %eax, %cr0
+
+ post_code(0x3a)
+
+#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
+ call soc_enable_mtrrs
+#else
+ /* Enable MTRR. */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ rdmsr
+ orl $MTRR_DEF_TYPE_EN, %eax
+ wrmsr
+#endif /* CONFIG_SOC_SETS_MTRRS */
+
+ post_code(0x3b)
+
+ /* Invalidate the cache again. */
+ invd
+
+ post_code(0x3c)
+
+__main:
+ post_code(POST_PREPARE_RAMSTAGE)
+ cld /* Clear direction flag. */
+ call after_cache_as_ram
+
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/cache_as_ram.inc b/src/vendorcode/intel/fsp/fsp1_1/common/cache_as_ram.inc
new file mode 100644
index 0000000..6e7e50b
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/cache_as_ram.inc
@@ -0,0 +1,225 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Replacement for cache_as_ram.inc when using the FSP binary. This code
+ * locates the FSP binary, initializes the cache as RAM and performs the
+ * first stage of initialization. Next this code switches the stack from
+ * the cache to RAM and then disables the cache as RAM. Finally this code
+ * performs the final stage of initialization.
+ */
+
+#include <rules.h>
+
+#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
+
+ /*
+ * eax: BIST value
+ * mm0: low 32-bits of TSC value
+ * mm1: high 32-bits of TSC value
+ */
+ movl %eax, %edi
+cache_as_ram:
+ post_code(0x20)
+
+#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
+
+ /*
+ * SOC specific setup
+ * NOTE: This has to preserve the registers
+ * mm0, mm1 and edi.
+ */
+ #include <soc/car_setup.S>
+
+ post_code(0x28)
+
+#endif
+
+ /*
+ * Find the FSP binary in cbfs.
+ * Make a fake stack that has the return value back to this code.
+ */
+ lea fake_fsp_stack, %esp
+ jmp find_fsp
+find_fsp_ret:
+ /* Save the FSP location */
+ mov %eax, %ebp
+
+ /*
+ * Only when a valid FSP binary is found at CONFIG_FSP_LOC is
+ * the returned FSP_INFO_HEADER structure address above the base
+ * address of FSP binary specified by the CONFIG_FSP_LOC value.
+ * All of the error values are in the 0x8xxxxxxx range which are
+ * below the CONFIG_FSP_LOC value.
+ */
+ cmp $CONFIG_FSP_LOC, %eax
+ jbe halt1
+
+ post_code(POST_FSP_TEMP_RAM_INIT)
+
+ /* Calculate entry into FSP */
+ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
+ add 0x1c(%ebp), %eax /* add in the offset for FSP */
+
+ /*
+ * Pass early init variables on a fake stack (no memory yet)
+ * as well as the return location
+ */
+ lea CAR_init_stack, %esp
+
+ /*
+ * BIST value is zero
+ * eax: TempRamInitApi address
+ * ebp: FSP_INFO_HEADER address
+ * edi: BIST value
+ * esi: Not used
+ * mm0: low 32-bits of TSC value
+ * mm1: high 32-bits of TSC value
+ */
+
+ /* call FSP binary to setup temporary stack */
+ jmp *%eax
+
+CAR_init_done:
+ addl $4, %esp
+
+ /*
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * edi: BIST value
+ * mm0: low 32-bits of TSC value
+ * mm1: high 32-bits of TSC value
+ */
+
+ cmp $0, %eax
+ jne halt2
+
+ /* Setup bootloader stack */
+ movl %edx, %esp
+
+ /*
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * edi: BIST value
+ * esp: Top of stack in temp RAM
+ * mm0: low 32-bits of TSC value
+ * mm1: high 32-bits of TSC value
+ */
+
+ /* Create cache_as_ram_params on stack */
+ pushl %edx /* bootloader CAR end */
+ pushl %ecx /* bootloader CAR begin */
+ pushl %ebp /* FSP_INFO_HEADER */
+ pushl %edi /* bist */
+ movd %mm1, %eax
+ pushl %eax /* tsc[63:32] */
+ movd %mm0, %eax
+ pushl %eax /* tsc[31:0] */
+ pushl %esp /* pointer to cache_as_ram_params */
+
+ /* Save FSP_INFO_HEADER location in ebx */
+ mov %ebp, %ebx
+
+ /* Coreboot assumes stack/heap region will be zero */
+ cld
+ movl %ecx, %edi
+ neg %ecx
+ /* Only clear up to current stack value. */
+ add %esp, %ecx
+ shrl $2, %ecx
+ xorl %eax, %eax
+ rep stosl
+
+before_romstage:
+ post_code(0x2A)
+
+ /* Call cache_as_ram_main(struct cache_as_ram_params *) */
+ call cache_as_ram_main
+
+/* One will never return from cache_as_ram_main() in verstage so there's
+ * no such thing as after ram init. */
+#if !ENV_VERSTAGE
+#include "after_raminit.S"
+#endif
+
+ movb $0x69, %ah
+ jmp .Lhlt
+
+halt1:
+ /*
+ * Failures for postcode 0xBA - failed in fsp_fih_early_find()
+ *
+ * Values are:
+ * 0x01 - FV signature, "_FVH" not present
+ * 0x02 - FFS GUID not present
+ * 0x03 - FSP INFO Header not found
+ * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
+ * a different location, or does it need to be?
+ * 0x05 - FSP INFO Header signature "FSPH" not found
+ * 0x06 - FSP Image ID is not the expected ID.
+ */
+ movb $0xBA, %ah
+ jmp .Lhlt
+
+halt2:
+ /*
+ * Failures for postcode 0xBB - failed in the FSP:
+ *
+ * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
+ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
+ * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
+ * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
+ * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
+ * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
+ */
+ movb $0xBB, %ah
+ jmp .Lhlt
+
+.Lhlt:
+ xchg %al, %ah
+#if IS_ENABLED(CONFIG_POST_IO)
+ outb %al, $CONFIG_POST_IO_PORT
+#else
+ post_code(POST_DEAD_CODE)
+#endif
+ movl $LHLT_DELAY, %ecx
+.Lhlt_Delay:
+ outb %al, $0xED
+ loop .Lhlt_Delay
+ jmp .Lhlt
+
+/*
+ * esp is set to this location so that the call into and return from the FSP
+ * in find_fsp will work.
+ */
+ .align 4
+fake_fsp_stack:
+ .long find_fsp_ret
+ .long CONFIG_FSP_LOC /* FSP base address */
+
+CAR_init_params:
+ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
+ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
+ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
+ .long CONFIG_ROM_SIZE /* Total Firmware Length */
+
+CAR_init_stack:
+ .long CAR_init_done
+ .long CAR_init_params
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/car.c b/src/vendorcode/intel/fsp/fsp1_1/common/car.c
new file mode 100644
index 0000000..b525a62
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/car.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <fsp/car.h>
+#include <fsp/util.h>
+#include <program_loading.h>
+#include <soc/intel/common/util.h>
+#include <timestamp.h>
+
+FSP_INFO_HEADER *fih_car CAR_GLOBAL;
+
+/* Save FSP_INFO_HEADER for TempRamExit() call in assembly. */
+static inline void set_fih_car(FSP_INFO_HEADER *fih)
+{
+ /* This variable is written in the raw form because it's only
+ * ever accessed in code that that has the cache-as-ram enabled. The
+ * assembly routine which tears down cache-as-ram utilizes this
+ * variable for determining where to find FSP. */
+ fih_car = fih;
+}
+
+asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
+{
+ /* Initialize timestamp book keeping only once. */
+ timestamp_init(car_params->tsc);
+
+ /* Call into pre-console init code then initialize console. */
+ car_soc_pre_console_init();
+ car_mainboard_pre_console_init();
+ console_init();
+
+ printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
+
+ printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
+ printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
+
+ if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE ||
+ car_params->bootloader_car_end !=
+ (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) {
+ printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n",
+ CONFIG_DCACHE_RAM_BASE,
+ CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE,
+ (long)car_params->bootloader_car_start,
+ (long)car_params->bootloader_car_end);
+ }
+
+ car_soc_post_console_init();
+ car_mainboard_post_console_init();
+
+ /* Ensure the EC is in the right mode for recovery */
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) &&
+ !IS_ENABLED(CONFIG_SEPARATE_VERSTAGE))
+ google_chromeec_early_init();
+
+ set_fih_car(car_params->fih);
+
+ /* Return new stack value in ram back to assembly stub. */
+ return cache_as_ram_stage_main(car_params->fih);
+}
+
+/* Entry point taken when romstage is called after a separate verstage. */
+asmlinkage void *romstage_after_verstage(void)
+{
+ /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
+ * is still enabled. We can directly access work buffer here. */
+ FSP_INFO_HEADER *fih;
+ struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
+
+ console_init();
+
+ if (prog_locate(&fsp)) {
+ fih = NULL;
+ printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp));
+ } else
+ /* This leaks a mapping which this code assumes is benign as
+ * the flash is memory mapped CPU's address space. */
+ fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp)));
+
+ set_fih_car(fih);
+
+ /* Return new stack value in ram back to assembly stub. */
+ return cache_as_ram_stage_main(fih);
+}
+
+asmlinkage void after_cache_as_ram(void *chipset_context)
+{
+ timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
+ printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
+ soc_display_mtrrs();
+
+ after_cache_as_ram_stage();
+}
+
+void __attribute__((weak)) car_mainboard_pre_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_soc_pre_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_mainboard_post_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_soc_post_console_init(void)
+{
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/fsp_gop.c b/src/vendorcode/intel/fsp/fsp1_1/common/fsp_gop.c
new file mode 100644
index 0000000..f531d76
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/fsp_gop.c
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <boot/coreboot_tables.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <lib.h>
+
+/* Reading VBT table from flash */
+const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len)
+{
+ size_t vbt_size;
+ union {
+ const optionrom_vbt_t *data;
+ uint32_t *signature;
+ } vbt;
+
+ /* Locate the vbt file in cbfs */
+ vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_OPTIONROM,
+ &vbt_size);
+ if (!vbt.data) {
+ printk(BIOS_INFO,
+ "FSP_INFO: VBT data file (vbt.bin) not found in CBFS");
+ return NULL;
+ }
+
+ /* Validate the vbt file */
+ if (*vbt.signature != VBT_SIGNATURE) {
+ printk(BIOS_WARNING,
+ "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n");
+ return NULL;
+ }
+ *vbt_len = vbt_size;
+ printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n",
+ vbt.data, *vbt_len);
+
+#if IS_ENABLED(CONFIG_DISPLAY_VBT)
+ /* Display the vbt file contents */
+ printk(BIOS_DEBUG, "VBT Data:\n");
+ hexdump(vbt.data, *vbt_len);
+ printk(BIOS_DEBUG, "\n");
+#endif
+
+ /* Return the pointer to the vbt file data */
+ return vbt.data;
+}
+
+void lb_framebuffer(struct lb_header *header)
+{
+ struct lb_framebuffer *framebuffer;
+ framebuffer = (struct lb_framebuffer *)lb_new_record(header);
+
+ VOID *hob_list_ptr;
+ hob_list_ptr = get_hob_list();
+ const EFI_GUID vbt_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
+ u32 *vbt_hob;
+ EFI_PEI_GRAPHICS_INFO_HOB *vbt_gop;
+ vbt_hob = get_next_guid_hob(&vbt_guid, hob_list_ptr);
+ if (vbt_hob == NULL) {
+ printk(BIOS_ERR, "FSP_ERR: Graphics Data HOB is not present\n");
+ return;
+ } else {
+ printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n");
+ vbt_gop = GET_GUID_HOB_DATA(vbt_hob);
+ }
+
+ framebuffer->physical_address = vbt_gop->FrameBufferBase;
+ framebuffer->x_resolution = vbt_gop->GraphicsMode.HorizontalResolution;
+ framebuffer->y_resolution = vbt_gop->GraphicsMode.VerticalResolution;
+ framebuffer->bytes_per_line = vbt_gop->GraphicsMode.PixelsPerScanLine
+ * 4;
+ framebuffer->bits_per_pixel = 32;
+ framebuffer->red_mask_pos = 16;
+ framebuffer->red_mask_size = 8;
+ framebuffer->green_mask_pos = 8;
+ framebuffer->green_mask_size = 8;
+ framebuffer->blue_mask_pos = 0;
+ framebuffer->blue_mask_size = 8;
+ framebuffer->reserved_mask_pos = 24;
+ framebuffer->reserved_mask_size = 8;
+ framebuffer->tag = LB_TAG_FRAMEBUFFER;
+ framebuffer->size = sizeof(*framebuffer);
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/fsp_relocate.c b/src/vendorcode/intel/fsp/fsp1_1/common/fsp_relocate.c
new file mode 100644
index 0000000..89d7cd9
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/fsp_relocate.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cbmem.h>
+#include <commonlib/fsp1_1.h>
+#include <fsp/util.h>
+
+int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src)
+{
+ void *new_loc;
+ void *fih;
+ ssize_t fih_offset;
+ size_t size = region_device_sz(fsp_src);
+
+ new_loc = cbmem_add(CBMEM_ID_REFCODE, size);
+
+ if (new_loc == NULL) {
+ printk(BIOS_ERR, "ERROR: Unable to load FSP into memory.\n");
+ return -1;
+ }
+
+ if (rdev_readat(fsp_src, new_loc, 0, size) != size) {
+ printk(BIOS_ERR, "ERROR: Can't read FSP's region device.\n");
+ return -1;
+ }
+
+ fih_offset = fsp1_1_relocate((uintptr_t)new_loc, new_loc, size);
+
+ if (fih_offset <= 0) {
+ printk(BIOS_ERR, "ERROR: FSP relocation faiulre.\n");
+ return -1;
+ }
+
+ fih = (void *)((uint8_t *)new_loc + fih_offset);
+
+ prog_set_area(fsp_relocd, new_loc, size);
+ prog_set_entry(fsp_relocd, fih, NULL);
+
+ return 0;
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/fsp_util.c b/src/vendorcode/intel/fsp/fsp1_1/common/fsp_util.c
new file mode 100644
index 0000000..1aa3aec
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/fsp_util.c
@@ -0,0 +1,299 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootstate.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <timestamp.h>
+
+/* Locate the FSP binary in the coreboot filesystem */
+FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address)
+{
+ union {
+ EFI_FFS_FILE_HEADER *ffh;
+ FSP_INFO_HEADER *fih;
+ EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh;
+ EFI_FIRMWARE_VOLUME_HEADER *fvh;
+ EFI_RAW_SECTION *rs;
+ u8 *u8;
+ u32 u32;
+ } fsp_ptr;
+ static const union {
+ char str_id[8];
+ u32 int_id[2];
+ } fsp_id = {
+ .str_id = CONFIG_FSP_IMAGE_ID_STRING
+ };
+
+ u32 *image_id;
+
+ for (;;) {
+ /* Get the FSP binary base address in CBFS */
+ fsp_ptr.u32 = fsp_base_address;
+
+ /* Check the FV signature, _FVH */
+ if (fsp_ptr.fvh->Signature != 0x4856465F) {
+ fsp_ptr.u8 = (u8 *)ERROR_NO_FV_SIG;
+ break;
+ }
+
+ /* Locate the file header which follows the FV header. */
+ fsp_ptr.u8 += fsp_ptr.fvh->ExtHeaderOffset;
+ fsp_ptr.u8 += fsp_ptr.fveh->ExtHeaderSize;
+ fsp_ptr.u8 = (u8 *)ALIGN_UP(fsp_ptr.u32, 8);
+
+ /* Check the FFS GUID */
+ if ((((u32 *)&fsp_ptr.ffh->Name)[0] != 0x912740BE)
+ || (((u32 *)&fsp_ptr.ffh->Name)[1] != 0x47342284)
+ || (((u32 *)&fsp_ptr.ffh->Name)[2] != 0xB08471B9)
+ || (((u32 *)&fsp_ptr.ffh->Name)[3] != 0x0C3F3527)) {
+ fsp_ptr.u8 = (u8 *)ERROR_NO_FFS_GUID;
+ break;
+ }
+
+ /* Locate the Raw Section Header */
+ fsp_ptr.u8 += sizeof(EFI_FFS_FILE_HEADER);
+
+ if (fsp_ptr.rs->Type != EFI_SECTION_RAW) {
+ fsp_ptr.u8 = (u8 *)ERROR_NO_INFO_HEADER;
+ break;
+ }
+
+ /* Locate the FSP INFO Header which follows the Raw Header. */
+ fsp_ptr.u8 += sizeof(EFI_RAW_SECTION);
+
+ /* Verify that the FSP base address.*/
+ if (fsp_ptr.fih->ImageBase != fsp_base_address) {
+ fsp_ptr.u8 = (u8 *)ERROR_IMAGEBASE_MISMATCH;
+ break;
+ }
+
+ /* Verify the FSP Signature */
+ if (fsp_ptr.fih->Signature != FSP_SIG) {
+ fsp_ptr.u8 = (u8 *)ERROR_INFO_HEAD_SIG_MISMATCH;
+ break;
+ }
+
+ /* Verify the FSP ID */
+ image_id = (u32 *)&fsp_ptr.fih->ImageId[0];
+ if ((image_id[0] != fsp_id.int_id[0])
+ || (image_id[1] != fsp_id.int_id[1]))
+ fsp_ptr.u8 = (u8 *)ERROR_FSP_SIG_MISMATCH;
+ break;
+ }
+
+ return fsp_ptr.fih;
+}
+
+void print_fsp_info(FSP_INFO_HEADER *fsp_header)
+{
+ u8 *fsp_base;
+
+ fsp_base = (u8 *)fsp_header->ImageBase;
+ printk(BIOS_SPEW, "FSP_INFO_HEADER: %p\n", fsp_header);
+ printk(BIOS_INFO, "FSP Signature: %c%c%c%c%c%c%c%c\n",
+ fsp_header->ImageId[0], fsp_header->ImageId[1],
+ fsp_header->ImageId[2], fsp_header->ImageId[3],
+ fsp_header->ImageId[4], fsp_header->ImageId[5],
+ fsp_header->ImageId[6], fsp_header->ImageId[7]);
+ printk(BIOS_INFO, "FSP Header Version: %d\n",
+ fsp_header->HeaderRevision);
+ printk(BIOS_INFO, "FSP Revision: %d.%d.%d.%d\n",
+ (u8)((fsp_header->ImageRevision >> 24) & 0xff),
+ (u8)((fsp_header->ImageRevision >> 16) & 0xff),
+ (u8)((fsp_header->ImageRevision >> 8) & 0xff),
+ (u8)(fsp_header->ImageRevision & 0xff));
+#if IS_ENABLED(CONFIG_DISPLAY_FSP_ENTRY_POINTS)
+ printk(BIOS_SPEW, "FSP Entry Points:\n");
+ printk(BIOS_SPEW, " 0x%p: Image Base\n", fsp_base);
+ printk(BIOS_SPEW, " 0x%p: TempRamInit\n",
+ &fsp_base[fsp_header->TempRamInitEntryOffset]);
+ printk(BIOS_SPEW, " 0x%p: FspInit\n",
+ &fsp_base[fsp_header->FspInitEntryOffset]);
+ if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) {
+ printk(BIOS_SPEW, " 0x%p: MemoryInit\n",
+ &fsp_base[fsp_header->FspMemoryInitEntryOffset]);
+ printk(BIOS_SPEW, " 0x%p: TempRamExit\n",
+ &fsp_base[fsp_header->TempRamExitEntryOffset]);
+ printk(BIOS_SPEW, " 0x%p: SiliconInit\n",
+ &fsp_base[fsp_header->FspSiliconInitEntryOffset]);
+ }
+ printk(BIOS_SPEW, " 0x%p: NotifyPhase\n",
+ &fsp_base[fsp_header->NotifyPhaseEntryOffset]);
+ printk(BIOS_SPEW, " 0x%p: Image End\n",
+ &fsp_base[fsp_header->ImageSize]);
+#endif
+}
+
+void fsp_notify(u32 phase)
+{
+ FSP_NOTIFY_PHASE notify_phase_proc;
+ NOTIFY_PHASE_PARAMS notify_phase_params;
+ EFI_STATUS status;
+ FSP_INFO_HEADER *fsp_header_ptr;
+
+ fsp_header_ptr = fsp_get_fih();
+ if (fsp_header_ptr == NULL) {
+ fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC);
+ if ((u32)fsp_header_ptr < 0xff) {
+ /* output something in case there is no serial */
+ post_code(0x4F);
+ die("Can't find the FSP!\n");
+ }
+ }
+
+ /* call FSP PEI to Notify PostPciEnumeration */
+ notify_phase_proc = (FSP_NOTIFY_PHASE)(fsp_header_ptr->ImageBase +
+ fsp_header_ptr->NotifyPhaseEntryOffset);
+ notify_phase_params.Phase = phase;
+
+ if (phase == EnumInitPhaseReadyToBoot) {
+ timestamp_add_now(TS_FSP_BEFORE_FINALIZE);
+ post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
+ } else {
+ timestamp_add_now(TS_FSP_BEFORE_ENUMERATE);
+ post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
+ }
+
+ status = notify_phase_proc(¬ify_phase_params);
+
+ timestamp_add_now(phase == EnumInitPhaseReadyToBoot ?
+ TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE);
+
+ if (status != 0)
+ printk(BIOS_ERR, "FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n",
+ phase, status);
+}
+
+static void fsp_notify_boot_state_callback(void *arg)
+{
+ u32 phase = (u32)arg;
+
+ printk(BIOS_SPEW, "Calling FspNotify(0x%08x)\n", phase);
+ fsp_notify(phase);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT,
+ fsp_notify_boot_state_callback,
+ (void *)EnumInitPhaseAfterPciEnumeration);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT,
+ fsp_notify_boot_state_callback,
+ (void *)EnumInitPhaseReadyToBoot);
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
+ fsp_notify_boot_state_callback,
+ (void *)EnumInitPhaseReadyToBoot);
+
+struct fsp_runtime {
+ uint32_t fih;
+ uint32_t hob_list;
+} __attribute__((packed));
+
+
+void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list)
+{
+ struct fsp_runtime *fspr;
+
+ fspr = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*fspr));
+
+ if (fspr == NULL)
+ die("Can't save FSP runtime information.\n");
+
+ fspr->fih = (uintptr_t)fih;
+ fspr->hob_list = (uintptr_t)hob_list;
+}
+
+FSP_INFO_HEADER *fsp_get_fih(void)
+{
+ struct fsp_runtime *fspr;
+
+ fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME);
+
+ if (fspr == NULL)
+ return NULL;
+
+ return (void *)(uintptr_t)fspr->fih;
+}
+
+void *fsp_get_hob_list(void)
+{
+ struct fsp_runtime *fspr;
+
+ fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME);
+
+ if (fspr == NULL)
+ return NULL;
+
+ return (void *)(uintptr_t)fspr->hob_list;
+}
+
+void fsp_update_fih(FSP_INFO_HEADER *fih)
+{
+ struct fsp_runtime *fspr;
+
+ fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME);
+
+ if (fspr == NULL)
+ die("Can't update FSP runtime information.\n");
+
+ fspr->fih = (uintptr_t)fih;
+}
+
+void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old,
+ uint64_t new)
+{
+ if (old == new) {
+ switch (size) {
+ case 1:
+ printk(BIOS_SPEW, " 0x%02llx: %s\n", new, name);
+ break;
+
+ case 2:
+ printk(BIOS_SPEW, " 0x%04llx: %s\n", new, name);
+ break;
+
+ case 4:
+ printk(BIOS_SPEW, " 0x%08llx: %s\n", new, name);
+ break;
+
+ case 8:
+ printk(BIOS_SPEW, " 0x%016llx: %s\n", new, name);
+ break;
+ }
+ } else {
+ switch (size) {
+ case 1:
+ printk(BIOS_SPEW, " 0x%02llx --> 0x%02llx: %s\n", old,
+ new, name);
+ break;
+
+ case 2:
+ printk(BIOS_SPEW, " 0x%04llx --> 0x%04llx: %s\n", old,
+ new, name);
+ break;
+
+ case 4:
+ printk(BIOS_SPEW, " 0x%08llx --> 0x%08llx: %s\n", old,
+ new, name);
+ break;
+
+ case 8:
+ printk(BIOS_SPEW, " 0x%016llx --> 0x%016llx: %s\n",
+ old, new, name);
+ break;
+ }
+ }
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/hob.c b/src/vendorcode/intel/fsp/fsp1_1/common/hob.c
new file mode 100644
index 0000000..c0816e9
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/hob.c
@@ -0,0 +1,325 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <arch/hlt.h>
+#include <bootstate.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <ip_checksum.h>
+#include <lib.h> // hexdump
+#include <string.h>
+
+/* Compares two EFI GUIDs. Returns true of the GUIDs match, false otherwise. */
+static bool compare_guid(const EFI_GUID *guid1, const EFI_GUID *guid2)
+{
+ return !memcmp(guid1, guid2, sizeof(EFI_GUID));
+}
+
+/* Returns the pointer to the HOB list. */
+void *get_hob_list(void)
+{
+ void *hob_list;
+
+ hob_list = fsp_get_hob_list();
+ if (hob_list == NULL)
+ die("Call fsp_set_runtime() before this call!\n");
+ return hob_list;
+}
+
+/* Returns the next instance of a HOB type from the starting HOB. */
+void *get_next_hob(uint16_t type, const void *hob_start)
+{
+ EFI_PEI_HOB_POINTERS hob;
+
+ if (!hob_start)
+ return NULL;
+
+ hob.Raw = (UINT8 *)hob_start;
+
+ /* Parse the HOB list until end of list or matching type is found. */
+ while (!END_OF_HOB_LIST(hob.Raw)) {
+ if (hob.Header->HobType == type)
+ return hob.Raw;
+ if (GET_HOB_LENGTH(hob.Raw) < sizeof(*hob.Header))
+ break;
+ hob.Raw = GET_NEXT_HOB(hob.Raw);
+ }
+ return NULL;
+}
+
+/* Returns the first instance of a HOB type among the whole HOB list. */
+void *get_first_hob(uint16_t type)
+{
+ return get_next_hob(type, get_hob_list());
+}
+
+/* Returns the next instance of the matched GUID HOB from the starting HOB. */
+void *get_next_guid_hob(const EFI_GUID * guid, const void *hob_start)
+{
+ EFI_PEI_HOB_POINTERS hob;
+
+ hob.Raw = (uint8_t *)hob_start;
+ while ((hob.Raw = get_next_hob(EFI_HOB_TYPE_GUID_EXTENSION, hob.Raw))
+ != NULL) {
+ if (compare_guid(guid, &hob.Guid->Name))
+ break;
+ hob.Raw = GET_NEXT_HOB(hob.Raw);
+ }
+ return hob.Raw;
+}
+
+/*
+ * Returns the first instance of the matched GUID HOB among the whole HOB list.
+ */
+void *get_first_guid_hob(const EFI_GUID *guid)
+{
+ return get_next_guid_hob(guid, get_hob_list());
+}
+
+/*
+ * Returns the next instance of the matching resource HOB from the starting HOB.
+ */
+void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start)
+{
+ EFI_PEI_HOB_POINTERS hob;
+
+ hob.Raw = (UINT8 *)hob_start;
+ while ((hob.Raw = get_next_hob(EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,
+ hob.Raw)) != NULL) {
+ if (compare_guid(guid, &hob.ResourceDescriptor->Owner))
+ break;
+ hob.Raw = GET_NEXT_HOB(hob.Raw);
+ }
+ return hob.Raw;
+}
+
+/*
+ * Returns the first instance of the matching resource HOB among the whole HOB
+ * list.
+ */
+void *get_first_resource_hob(const EFI_GUID *guid)
+{
+ return get_next_resource_hob(guid, get_hob_list());
+}
+
+static void print_hob_mem_attributes(void *hob_ptr)
+{
+ EFI_MEMORY_TYPE hob_mem_type;
+ EFI_HOB_MEMORY_ALLOCATION *hob_memory_ptr = hob_ptr;
+ u64 hob_mem_addr = hob_memory_ptr->AllocDescriptor.MemoryBaseAddress;
+ u64 hob_mem_length = hob_memory_ptr->AllocDescriptor.MemoryLength;
+
+ hob_mem_type = hob_memory_ptr->AllocDescriptor.MemoryType;
+
+ static const char *hob_mem_type_names[15] = {
+ [EfiReservedMemoryType] = "EfiReservedMemoryType",
+ [EfiLoaderCode] = "EfiLoaderCode",
+ [EfiLoaderData] = "EfiLoaderData",
+ [EfiBootServicesCode] = "EfiBootServicesCode",
+ [EfiBootServicesData] = "EfiBootServicesData",
+ [EfiRuntimeServicesCode] = "EfiRuntimeServicesCode",
+ [EfiRuntimeServicesData] = "EfiRuntimeServicesData",
+ [EfiConventionalMemory] = "EfiConventionalMemory",
+ [EfiUnusableMemory] = "EfiUnusableMemory",
+ [EfiACPIReclaimMemory] = "EfiACPIReclaimMemory",
+ [EfiACPIMemoryNVS] = "EfiACPIMemoryNVS",
+ [EfiMemoryMappedIO] = "EfiMemoryMappedIO",
+ [EfiMemoryMappedIOPortSpace] = "EfiMemoryMappedIOPortSpace",
+ [EfiPalCode] = "EfiPalCode",
+ [EfiMaxMemoryType] = "EfiMaxMemoryType",
+ };
+
+ if (hob_mem_type >= ARRAY_SIZE(hob_mem_type_names))
+ hob_mem_type = EfiReservedMemoryType;
+
+ printk(BIOS_SPEW, " Memory type %s (0x%x)\n",
+ hob_mem_type_names[hob_mem_type],
+ (u32)hob_mem_type);
+ printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n",
+ (unsigned long)hob_mem_addr,
+ (unsigned long)hob_mem_length);
+}
+
+static void print_hob_resource_attributes(void *hob_ptr)
+{
+ EFI_HOB_RESOURCE_DESCRIPTOR *hob_resource_ptr =
+ (EFI_HOB_RESOURCE_DESCRIPTOR *)hob_ptr;
+ u32 hob_res_type = hob_resource_ptr->ResourceType;
+ u32 hob_res_attr = hob_resource_ptr->ResourceAttribute;
+ u64 hob_res_addr = hob_resource_ptr->PhysicalStart;
+ u64 hob_res_length = hob_resource_ptr->ResourceLength;
+ const char *hob_res_type_str = NULL;
+
+ /* HOB Resource Types */
+ switch (hob_res_type) {
+ case EFI_RESOURCE_SYSTEM_MEMORY:
+ hob_res_type_str = "EFI_RESOURCE_SYSTEM_MEMORY";
+ break;
+ case EFI_RESOURCE_MEMORY_MAPPED_IO:
+ hob_res_type_str = "EFI_RESOURCE_MEMORY_MAPPED_IO";
+ break;
+ case EFI_RESOURCE_IO:
+ hob_res_type_str = "EFI_RESOURCE_IO";
+ break;
+ case EFI_RESOURCE_FIRMWARE_DEVICE:
+ hob_res_type_str = "EFI_RESOURCE_FIRMWARE_DEVICE";
+ break;
+ case EFI_RESOURCE_MEMORY_MAPPED_IO_PORT:
+ hob_res_type_str = "EFI_RESOURCE_MEMORY_MAPPED_IO_PORT";
+ break;
+ case EFI_RESOURCE_MEMORY_RESERVED:
+ hob_res_type_str = "EFI_RESOURCE_MEMORY_RESERVED";
+ break;
+ case EFI_RESOURCE_IO_RESERVED:
+ hob_res_type_str = "EFI_RESOURCE_IO_RESERVED";
+ break;
+ case EFI_RESOURCE_MAX_MEMORY_TYPE:
+ hob_res_type_str = "EFI_RESOURCE_MAX_MEMORY_TYPE";
+ break;
+ default:
+ hob_res_type_str = "EFI_RESOURCE_UNKNOWN";
+ break;
+ }
+
+ printk(BIOS_SPEW, " Resource %s (0x%0x) has attributes 0x%0x\n",
+ hob_res_type_str, hob_res_type, hob_res_attr);
+ printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n",
+ (unsigned long)hob_res_addr,
+ (unsigned long)hob_res_length);
+}
+
+static const char *get_hob_type_string(void *hob_ptr)
+{
+ EFI_PEI_HOB_POINTERS hob;
+ const char *hob_type_string;
+ const EFI_GUID fsp_reserved_guid =
+ FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID;
+ const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+ const EFI_GUID bootldr_tmp_mem_guid =
+ FSP_BOOTLOADER_TEMP_MEMORY_HOB_GUID;
+ const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
+ const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
+ const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
+
+ hob.Header = (EFI_HOB_GENERIC_HEADER *)hob_ptr;
+ switch (hob.Header->HobType) {
+ case EFI_HOB_TYPE_HANDOFF:
+ hob_type_string = "EFI_HOB_TYPE_HANDOFF";
+ break;
+ case EFI_HOB_TYPE_MEMORY_ALLOCATION:
+ hob_type_string = "EFI_HOB_TYPE_MEMORY_ALLOCATION";
+ break;
+ case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
+ if (compare_guid(&fsp_reserved_guid, &hob.Guid->Name))
+ hob_type_string = "FSP_RESERVED_MEMORY_RESOURCE_HOB";
+ else if (compare_guid(&bootldr_tolum_guid, &hob.Guid->Name))
+ hob_type_string = "FSP_BOOTLOADER_TOLUM_HOB_GUID";
+ else
+ hob_type_string = "EFI_HOB_TYPE_RESOURCE_DESCRIPTOR";
+ break;
+ case EFI_HOB_TYPE_GUID_EXTENSION:
+ if (compare_guid(&bootldr_tmp_mem_guid, &hob.Guid->Name))
+ hob_type_string = "FSP_BOOTLOADER_TEMP_MEMORY_HOB";
+ else if (compare_guid(&mrc_guid, &hob.Guid->Name))
+ hob_type_string = "FSP_NON_VOLATILE_STORAGE_HOB";
+ else if (compare_guid(&graphics_info_guid, &hob.Guid->Name))
+ hob_type_string = "EFI_PEI_GRAPHICS_INFO_HOB_GUID";
+ else if (compare_guid(&memory_info_hob_guid, &hob.Guid->Name))
+ hob_type_string = "FSP_SMBIOS_MEMORY_INFO_GUID";
+ else
+ hob_type_string = "EFI_HOB_TYPE_GUID_EXTENSION";
+ break;
+ case EFI_HOB_TYPE_MEMORY_POOL:
+ hob_type_string = "EFI_HOB_TYPE_MEMORY_POOL";
+ break;
+ case EFI_HOB_TYPE_UNUSED:
+ hob_type_string = "EFI_HOB_TYPE_UNUSED";
+ break;
+ case EFI_HOB_TYPE_END_OF_HOB_LIST:
+ hob_type_string = "EFI_HOB_TYPE_END_OF_HOB_LIST";
+ break;
+ default:
+ hob_type_string = "EFI_HOB_TYPE_UNRECOGNIZED";
+ break;
+ }
+
+ return hob_type_string;
+}
+
+/*
+ * Print out a structure of all the HOBs
+ * that match a certain type:
+ * Print all types (0x0000)
+ * EFI_HOB_TYPE_HANDOFF (0x0001)
+ * EFI_HOB_TYPE_MEMORY_ALLOCATION (0x0002)
+ * EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (0x0003)
+ * EFI_HOB_TYPE_GUID_EXTENSION (0x0004)
+ * EFI_HOB_TYPE_MEMORY_POOL (0x0007)
+ * EFI_HOB_TYPE_UNUSED (0xFFFE)
+ * EFI_HOB_TYPE_END_OF_HOB_LIST (0xFFFF)
+ */
+void print_hob_type_structure(u16 hob_type, void *hob_list_ptr)
+{
+ u32 *current_hob;
+ u32 *next_hob = 0;
+ u8 last_hob = 0;
+ u32 current_type;
+ const char *current_type_str;
+
+ current_hob = hob_list_ptr;
+
+ /*
+ * Print out HOBs of our desired type until
+ * the end of the HOB list
+ */
+ printk(BIOS_DEBUG, "\n=== FSP HOB Data Structure ===\n");
+ printk(BIOS_DEBUG, "0x%p: hob_list_ptr\n", hob_list_ptr);
+ do {
+ EFI_HOB_GENERIC_HEADER *current_header_ptr =
+ (EFI_HOB_GENERIC_HEADER *)current_hob;
+
+ /* Get the type of this HOB */
+ current_type = current_header_ptr->HobType;
+ current_type_str = get_hob_type_string(current_hob);
+
+ if (current_type == hob_type || hob_type == 0x0000) {
+ printk(BIOS_DEBUG, "HOB %p is an %s (type 0x%0x)\n",
+ current_hob, current_type_str,
+ current_type);
+ switch (current_type) {
+ case EFI_HOB_TYPE_MEMORY_ALLOCATION:
+ print_hob_mem_attributes(current_hob);
+ break;
+ case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
+ print_hob_resource_attributes(current_hob);
+ break;
+ }
+ }
+
+ /* Check for end of HOB list */
+ last_hob = END_OF_HOB_LIST(current_hob);
+ if (!last_hob) {
+ /* Get next HOB pointer */
+ next_hob = GET_NEXT_HOB(current_hob);
+
+ /* Start on next HOB */
+ current_hob = next_hob;
+ }
+ } while (!last_hob);
+ printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n");
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/api.h b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/api.h
new file mode 100644
index 0000000..773b3c3
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/api.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _FSP1_1_API_H_
+#define _FSP1_1_API_H_
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h>
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/car.h b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/car.h
new file mode 100644
index 0000000..56400a7
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/car.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef FSP1_1_CAR_H
+#define FSP1_1_CAR_H
+
+#include <arch/cpu.h>
+#include <fsp/api.h>
+#include <stdint.h>
+
+/* cache-as-ram support for FSP 1.1. */
+struct cache_as_ram_params {
+ uint64_t tsc;
+ uint32_t bist;
+ FSP_INFO_HEADER *fih;
+ uintptr_t bootloader_car_start;
+ uintptr_t bootloader_car_end;
+};
+
+/* Entry points from the cache-as-ram assembly code. */
+asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
+asmlinkage void after_cache_as_ram(void *chipset_context);
+asmlinkage void *romstage_after_verstage(void);
+/* Per stage calls from the above two functions. The void * return from
+ * cache_as_ram_stage_main() is the stack pointer to use in ram after
+ * exiting cache-as-ram mode. */
+void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih);
+void after_cache_as_ram_stage(void);
+
+/* Mainboard and SoC initialization prior to console. */
+void car_mainboard_pre_console_init(void);
+void car_soc_pre_console_init(void);
+/* Mainboard and SoC initialization post console initialization. */
+void car_mainboard_post_console_init(void);
+void car_soc_post_console_init(void);
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/gma.h b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/gma.h
new file mode 100644
index 0000000..8797932
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/gma.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Chromium OS Authors
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _GMA_H_
+#define _GMA_H_
+
+#include <types.h>
+
+/* IGD PCI Configuration register */
+#define ASLS 0xfc /* OpRegion Base */
+#define SWSCI 0xe8 /* SWSCI Register */
+#define GSSCIE (1 << 0) /* SCI Event trigger */
+#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */
+
+/* mailbox 0: header */
+typedef struct {
+ u8 signature[16];
+ u32 size;
+ u32 version;
+ u8 sbios_version[32];
+ u8 vbios_version[16];
+ u8 driver_version[16];
+ u32 mailboxes;
+ u8 reserved[164];
+} __attribute__((packed)) opregion_header_t;
+
+#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
+#define IGD_OPREGION_VERSION 2
+
+#define IGD_MBOX1 (1 << 0)
+#define IGD_MBOX2 (1 << 1)
+#define IGD_MBOX3 (1 << 2)
+#define IGD_MBOX4 (1 << 3)
+#define IGD_MBOX5 (1 << 4)
+
+#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
+ IGD_MBOX4 | IGD_MBOX5)
+#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
+
+#define SBIOS_VERSION_SIZE 32
+
+/* mailbox 1: public acpi methods */
+typedef struct {
+ u32 drdy;
+ u32 csts;
+ u32 cevt;
+ u8 reserved1[20];
+ u32 didl[8];
+ u32 cpdl[8];
+ u32 cadl[8];
+ u32 nadl[8];
+ u32 aslp;
+ u32 tidx;
+ u32 chpd;
+ u32 clid;
+ u32 cdck;
+ u32 sxsw;
+ u32 evts;
+ u32 cnot;
+ u32 nrdy;
+ u8 reserved2[60];
+} __attribute__((packed)) opregion_mailbox1_t;
+
+/* mailbox 2: software sci interface */
+typedef struct {
+ u32 scic;
+ u32 parm;
+ u32 dslp;
+ u8 reserved[244];
+} __attribute__((packed)) opregion_mailbox2_t;
+
+/* mailbox 3: power conservation */
+typedef struct {
+ u32 ardy;
+ u32 aslc;
+ u32 tche;
+ u32 alsi;
+ u32 bclp;
+ u32 pfit;
+ u32 cblv;
+ u16 bclm[20];
+ u32 cpfm;
+ u32 epfm;
+ u8 plut[74];
+ u32 pfmb;
+ u32 ccdv;
+ u32 pcft;
+ u8 reserved[94];
+} __attribute__((packed)) opregion_mailbox3_t;
+
+#define IGD_BACKLIGHT_BRIGHTNESS 0xff
+#define IGD_INITIAL_BRIGHTNESS 0x64
+
+#define IGD_FIELD_VALID (1 << 31)
+#define IGD_WORD_FIELD_VALID (1 << 15)
+#define IGD_PFIT_STRETCH 6
+
+/* mailbox 4: vbt */
+typedef struct {
+ u8 gvd1[7168];
+} __attribute__((packed)) opregion_vbt_t;
+
+/* IGD OpRegion */
+typedef struct {
+ opregion_header_t header;
+ opregion_mailbox1_t mailbox1;
+ opregion_mailbox2_t mailbox2;
+ opregion_mailbox3_t mailbox3;
+ opregion_vbt_t vbt;
+} __attribute__((packed)) igd_opregion_t;
+
+/* Intel Video BIOS (Option ROM) */
+typedef struct {
+ u16 signature;
+ u8 size;
+ u8 reserved[21];
+ u16 pcir_offset;
+ u16 vbt_offset;
+} __attribute__((packed)) optionrom_header_t;
+
+#define OPROM_SIGNATURE 0xaa55
+
+typedef struct {
+ u32 signature;
+ u16 vendor;
+ u16 device;
+ u16 reserved1;
+ u16 length;
+ u8 revision;
+ u8 classcode[3];
+ u16 imagelength;
+ u16 coderevision;
+ u8 codetype;
+ u8 indicator;
+ u16 reserved2;
+} __attribute__((packed)) optionrom_pcir_t;
+
+typedef struct {
+ u8 hdr_signature[20];
+ u16 hdr_version;
+ u16 hdr_size;
+ u16 hdr_vbt_size;
+ u8 hdr_vbt_checksum;
+ u8 hdr_reserved;
+ u32 hdr_vbt_datablock;
+ u32 hdr_aim[4];
+ u8 datahdr_signature[16];
+ u16 datahdr_version;
+ u16 datahdr_size;
+ u16 datahdr_datablocksize;
+ u8 coreblock_id;
+ u16 coreblock_size;
+ u16 coreblock_biossize;
+ u8 coreblock_biostype;
+ u8 coreblock_releasestatus;
+ u8 coreblock_hwsupported;
+ u8 coreblock_integratedhw;
+ u8 coreblock_biosbuild[4];
+ u8 coreblock_biossignon[155];
+} __attribute__((packed)) optionrom_vbt_t;
+
+#define VBT_SIGNATURE 0x54425624
+
+#endif /* _GMA_H_ */
+
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/gop.h b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/gop.h
new file mode 100644
index 0000000..66c8a3c
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/gop.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _FSP1_1_GOP_H_
+#define _FSP1_1_GOP_H_
+
+#include <fsp/gma.h>
+
+const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
+
+#endif /* _FSP1_1_GOP_H_ */
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/memmap.h b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/memmap.h
new file mode 100644
index 0000000..965bce6
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/memmap.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _COMMON_MEMMAP_H_
+#define _COMMON_MEMMAP_H_
+
+#include <types.h>
+
+/*
+ * mmap_region_granularity must to return a size which is a positive non-zero
+ * integer multiple of the SMM size when SMM is in use. When not using SMM,
+ * this value should be set to 8 MiB.
+ */
+size_t mmap_region_granularity(void);
+
+/* Fills in the arguments for the entire SMM region covered by chipset
+ * protections. e.g. TSEG. */
+void smm_region(void **start, size_t *size);
+
+enum {
+ /* SMM handler area. */
+ SMM_SUBREGION_HANDLER,
+ /* SMM cache region. */
+ SMM_SUBREGION_CACHE,
+ /* Chipset specific area. */
+ SMM_SUBREGION_CHIPSET,
+ /* Total sub regions supported. */
+ SMM_SUBREGION_NUM,
+};
+
+/* Fills in the start and size for the requested SMM subregion. Returns
+ * 0 on susccess, < 0 on failure. */
+int smm_subregion(int sub, void **start, size_t *size);
+
+#endif /* _COMMON_MEMMAP_H_ */
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/ramstage.h b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/ramstage.h
new file mode 100644
index 0000000..5ce6aa8
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/ramstage.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _INTEL_COMMON_RAMSTAGE_H_
+#define _INTEL_COMMON_RAMSTAGE_H_
+
+#include <fsp/util.h>
+#include <soc/intel/common/util.h>
+#include <stdint.h>
+
+/* Perform Intel silicon init. */
+void intel_silicon_init(void);
+void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup);
+/* Called after the silicon init code has run. */
+void soc_after_silicon_init(void);
+/* Initialize UPD data before SiliconInit call. */
+void soc_silicon_init_params(SILICON_INIT_UPD *params);
+void mainboard_silicon_init_params(SILICON_INIT_UPD *params);
+void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
+ SILICON_INIT_UPD *new);
+void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params);
+
+#endif /* _INTEL_COMMON_RAMSTAGE_H_ */
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/romstage.h b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/romstage.h
new file mode 100644
index 0000000..d07dc37
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/romstage.h
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _COMMON_ROMSTAGE_H_
+#define _COMMON_ROMSTAGE_H_
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <memory_info.h>
+#include <fsp/car.h>
+#include <fsp/util.h>
+#include <soc/intel/common/util.h>
+#include <soc/pei_wrapper.h>
+#include <soc/pm.h> /* chip_power_state */
+
+struct romstage_params {
+ uint32_t fsp_version;
+ struct chipset_power_state *power_state;
+ struct pei_data *pei_data;
+ void *chipset_context;
+};
+
+/*
+ * FSP Boot Flow:
+ * 1. src/cpu/x86/16bit/reset.inc
+ * 2. src/cpu/x86/16bit/entry.inc
+ * 3. other modules
+ * 4. src/drivers/intel/fsp1_1/cache_as_ram.inc
+ * 5. src/drivers/intel/fsp1_1/fsp_util.c/find_fsp
+ * 6. FSP binary/TempRamInit
+ * 7. src/drivers/intel/fsp1_1/cache_as_ram.inc - return
+ * 8. src/soc/intel/common/romstage.c/romstage_main
+ * 9 src/soc/.../romstage/.../soc_pre_console_init
+ * 10 src/console/console.c/console_init
+ * 11 src/soc/.../romstage/.../soc_romstage_init
+ * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry
+ * 13. src/soc/intel/common/romstage.c/romstage_common
+ * 14 src/soc/.../romstage/.../soc_pre_raminit
+ * 15. FSP binary/MemoryInit
+ * 16. src/soc/intel/common/romstage.c/romstage_common - return
+ * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return
+ * 18. src/soc/intel/common/romstage.c/romstage_main - return
+ * 19. src/soc/intel/common/stack.c/setup_stack_and_mttrs
+ * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup
+ * after call to romstage_main
+ * 21. FSP binary/TempRamExit
+ * 22. src/soc/intel/common/romstage.c/romstage_after_car
+ * 23. FSP binary/SiliconInit
+ * 24. src/soc/intel/common/romstage.c/romstage_after_car - return
+ * 25. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
+ * 26. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
+ * 27. FSP binary/FspNotify
+ * 28. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
+ * 29. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
+ * 30. FSP binary/FspNotify
+ */
+
+void mainboard_check_ec_image(struct romstage_params *params);
+void mainboard_memory_init_params(struct romstage_params *params,
+ MEMORY_INIT_UPD *memory_params);
+void mainboard_romstage_entry(struct romstage_params *params);
+void mainboard_save_dimm_info(struct romstage_params *params);
+void mainboard_add_dimm_info(struct romstage_params *params,
+ struct memory_info *mem_info,
+ int channel, int dimm, int index);
+void raminit(struct romstage_params *params);
+void report_memory_config(void);
+void romstage_common(struct romstage_params *params);
+asmlinkage void *romstage_main(FSP_INFO_HEADER *fih);
+void *setup_stack_and_mtrrs(void);
+void soc_after_ram_init(struct romstage_params *params);
+void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
+ MEMORY_INIT_UPD *new);
+void soc_memory_init_params(struct romstage_params *params,
+ MEMORY_INIT_UPD *upd);
+void soc_pre_ram_init(struct romstage_params *params);
+
+/*
+ * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs.
+ * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data.
+ */
+asmlinkage void *soc_set_mtrrs(void *top_of_stack);
+asmlinkage void soc_enable_mtrrs(void);
+
+#endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/soc_binding.h b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/soc_binding.h
new file mode 100644
index 0000000..affb43f
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/soc_binding.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _FSP1_1_SOC_BINDING_H_
+#define _FSP1_1_SOC_BINDING_H_
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * This file is found in the soc / chipset directory. It is
+ * a per implementation specific header. i.e. different FSP implementations
+ * for different chipsets.
+ */
+#include <FspUpdVpd.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/stack.h b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/stack.h
new file mode 100644
index 0000000..e60360d
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/stack.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _COMMON_STACK_H_
+#define _COMMON_STACK_H_
+
+#include <stdint.h>
+
+static inline void *stack_push32(void *stack, uint32_t value)
+{
+ uint32_t *stack32 = stack;
+
+ stack32 = &stack32[-1];
+ *stack32 = value;
+ return stack32;
+}
+
+#endif /* _COMMON_STACK_H_ */
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/uefi_binding.h b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/uefi_binding.h
new file mode 100644
index 0000000..ad5bd36
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/uefi_binding.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _FSP1_1_UEFI_BINDING_H_
+#define _FSP1_1_UEFI_BINDING_H_
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * Pull in the UEFI types from 2.4. Smarter decisions can be made on what
+ * version to bind to, but for now 2.4 is standard for FSP 1.1.
+ */
+#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/util.h b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/util.h
new file mode 100644
index 0000000..07cf0c7
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/include/fsp/util.h
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef FSP1_1_UTIL_H
+#define FSP1_1_UTIL_H
+
+#include <rules.h>
+#include <fsp/api.h>
+/* Current users expect to get the SoC's FSP definitions by including util.h. */
+#include <fsp/soc_binding.h>
+#include <fsp/gop.h>
+#include <program_loading.h>
+#include <commonlib/region.h>
+
+/* find_fsp() should only be called from assembly code. */
+FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
+/* Set FSP's runtime information. */
+void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list);
+/* Use a new FSP_INFO_HEADER at runtime. */
+void fsp_update_fih(FSP_INFO_HEADER *fih);
+/* fsp_get_fih() is only valid after calling fsp_set_runtime(). */
+FSP_INFO_HEADER *fsp_get_fih(void);
+/* fsp_get_hob_list() is only valid after calling fsp_set_runtime(). */
+void *fsp_get_hob_list(void);
+void fsp_early_init(FSP_INFO_HEADER *fsp_info);
+void fsp_notify(u32 phase);
+void print_hob_type_structure(u16 hob_type, void *hob_list_ptr);
+void print_fsp_info(FSP_INFO_HEADER *fsp_header);
+void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid,
+ const void *hob_start);
+void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
+void *get_first_resource_hob(const EFI_GUID *guid);
+void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old,
+ uint64_t new);
+
+/* Return version of FSP associated with fih. */
+static inline uint32_t fsp_version(FSP_INFO_HEADER *fih)
+{
+ return fih->ImageRevision;
+}
+
+/*
+ * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success.
+ * The FSP source is pointed to by region_device and the relocation information
+ * is encoded in a struct prog with its entry point set to the FSP info header.
+ */
+int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
+
+/* Additional HOB types not included in the FSP:
+ * #define EFI_HOB_TYPE_HANDOFF 0x0001
+ * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
+ * #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
+ * #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
+ * #define EFI_HOB_TYPE_FV 0x0005
+ * #define EFI_HOB_TYPE_CPU 0x0006
+ * #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
+ * #define EFI_HOB_TYPE_CV 0x0008
+ * #define EFI_HOB_TYPE_UNUSED 0xFFFE
+ * #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff
+ */
+#define EFI_HOB_TYPE_HANDOFF 0x0001
+#define EFI_HOB_TYPE_MEMORY_POOL 0x0007
+
+/* The offset in bytes from the start of the info structure */
+#define FSP_IMAGE_SIG_LOC 0
+#define FSP_IMAGE_ID_LOC 16
+#define FSP_IMAGE_BASE_LOC 28
+#define FSP_IMAGE_ATTRIBUTE_LOC 32
+#define GRAPHICS_SUPPORT_BIT (1 << 0)
+
+#define ERROR_NO_FV_SIG 1
+#define ERROR_NO_FFS_GUID 2
+#define ERROR_NO_INFO_HEADER 3
+#define ERROR_IMAGEBASE_MISMATCH 4
+#define ERROR_INFO_HEAD_SIG_MISMATCH 5
+#define ERROR_FSP_SIG_MISMATCH 6
+
+#if ENV_RAMSTAGE
+extern void *FspHobListPtr;
+#endif
+
+/* TODO: Remove the EFI types and decorations from coreboot implementations. */
+VOID * EFIAPI get_hob_list(VOID);
+VOID * EFIAPI get_next_hob(UINT16 type, CONST VOID *hob_start);
+VOID * EFIAPI get_first_hob(UINT16 type);
+VOID * EFIAPI get_next_guid_hob(CONST EFI_GUID * guid, CONST VOID *hob_start);
+VOID * EFIAPI get_first_guid_hob(CONST EFI_GUID * guid);
+
+#endif /* FSP1_1_UTIL_H */
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/raminit.c b/src/vendorcode/intel/fsp/fsp1_1/common/raminit.c
new file mode 100644
index 0000000..e505b93
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/raminit.c
@@ -0,0 +1,320 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp/memmap.h>
+#include <fsp/romstage.h>
+#include <fsp/util.h>
+#include <lib.h> /* hexdump */
+#include <reset.h>
+#include <soc/intel/common/mma.h>
+#include <string.h>
+#include <timestamp.h>
+#include <bootmode.h>
+
+void raminit(struct romstage_params *params)
+{
+ const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
+ EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root;
+ FSP_INFO_HEADER *fsp_header;
+ EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory;
+ FSP_MEMORY_INIT fsp_memory_init;
+ FSP_MEMORY_INIT_PARAMS fsp_memory_init_params;
+ const EFI_GUID fsp_reserved_guid =
+ FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID;
+ void *fsp_reserved_memory_area;
+ FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer;
+ void *hob_list_ptr;
+ FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
+ const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
+ MEMORY_INIT_UPD memory_init_params;
+ const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+ u32 *mrc_hob;
+ u32 fsp_reserved_bytes;
+ MEMORY_INIT_UPD *original_params;
+ struct pei_data *pei_ptr;
+ EFI_STATUS status;
+ VPD_DATA_REGION *vpd_ptr;
+ UPD_DATA_REGION *upd_ptr;
+ int fsp_verification_failure = 0;
+#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+ unsigned long int data;
+ EFI_PEI_HOB_POINTERS hob_ptr;
+#endif
+
+ /*
+ * Find and copy the UPD region to the stack so the platform can modify
+ * the settings if needed. Modifications to the UPD buffer are done in
+ * the platform callback code. The platform callback code is also
+ * responsible for assigning the UpdDataRngPtr to this buffer if any
+ * updates are made. The default state is to leave the UpdDataRngPtr
+ * set to NULL. This indicates that the FSP code will use the UPD
+ * region in the FSP binary.
+ */
+ post_code(0x34);
+ fsp_header = params->chipset_context;
+ vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
+ fsp_header->ImageBase);
+ printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr);
+ upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
+ fsp_header->ImageBase);
+ printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr);
+ original_params = (void *)((u8 *)upd_ptr +
+ upd_ptr->MemoryInitUpdOffset);
+ memcpy(&memory_init_params, original_params,
+ sizeof(memory_init_params));
+
+ /* Zero fill RT Buffer data and start populating fields. */
+ memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer));
+ pei_ptr = params->pei_data;
+ if (pei_ptr->boot_mode == SLEEP_STATE_S3) {
+ fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME;
+ } else if (pei_ptr->saved_data != NULL) {
+ fsp_rt_common_buffer.BootMode =
+ BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
+ } else {
+ fsp_rt_common_buffer.BootMode = BOOT_WITH_FULL_CONFIGURATION;
+ }
+ fsp_rt_common_buffer.UpdDataRgnPtr = &memory_init_params;
+ fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size();
+
+ /* Get any board specific changes */
+ fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data;
+ fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer;
+ fsp_memory_init_params.HobListPtr = &hob_list_ptr;
+
+ /* Update the UPD data */
+ soc_memory_init_params(params, &memory_init_params);
+ mainboard_memory_init_params(params, &memory_init_params);
+
+ if (IS_ENABLED(CONFIG_MMA))
+ setup_mma(&memory_init_params);
+
+ post_code(0x36);
+
+ /* Display the UPD data */
+ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
+ soc_display_memory_init_params(original_params,
+ &memory_init_params);
+
+ /* Call FspMemoryInit to initialize RAM */
+ fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase
+ + fsp_header->FspMemoryInitEntryOffset);
+ printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init);
+ printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n",
+ fsp_memory_init_params.NvsBufferPtr);
+ printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n",
+ fsp_memory_init_params.RtBufferPtr);
+ printk(BIOS_SPEW, " 0x%p: HobListPtr\n",
+ fsp_memory_init_params.HobListPtr);
+
+ timestamp_add_now(TS_FSP_MEMORY_INIT_START);
+ post_code(POST_FSP_MEMORY_INIT);
+ status = fsp_memory_init(&fsp_memory_init_params);
+ post_code(0x37);
+ timestamp_add_now(TS_FSP_MEMORY_INIT_END);
+
+ printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
+ if (status != EFI_SUCCESS)
+ die("ERROR - FspMemoryInit failed to initialize memory!\n");
+
+ /* Locate the FSP reserved memory area */
+ fsp_reserved_bytes = 0;
+ fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr);
+ if (fsp_memory == NULL) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG,
+ "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n");
+ } else {
+ fsp_reserved_bytes = fsp_memory->ResourceLength;
+ printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n",
+ (unsigned long int)fsp_reserved_bytes);
+ }
+
+ /* Display SMM area */
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ char *smm_base;
+ size_t smm_size;
+
+ smm_region((void **)&smm_base, &smm_size);
+ printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size);
+ printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base);
+#endif
+
+ /* Migrate CAR data */
+ printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
+ if (pei_ptr->boot_mode != SLEEP_STATE_S3) {
+ cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
+ fsp_reserved_bytes);
+ } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
+ fsp_reserved_bytes)) {
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+ printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+ /* Failed S3 resume, reset to come up cleanly */
+ hard_reset();
+#endif
+ }
+
+ /* Save the FSP runtime parameters. */
+ fsp_set_runtime(fsp_header, hob_list_ptr);
+
+ /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */
+ cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr);
+ if (cbmem_root == NULL) {
+ fsp_verification_failure = 1;
+ printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n");
+ printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n",
+ fsp_rt_common_buffer.BootLoaderTolumSize);
+ }
+
+ /* Locate the FSP_SMBIOS_MEMORY_INFO HOB */
+ memory_info_hob = get_next_guid_hob(&memory_info_hob_guid,
+ hob_list_ptr);
+ if (NULL == memory_info_hob) {
+ printk(BIOS_ERR, "FSP_SMBIOS_MEMORY_INFO HOB missing!\n");
+ fsp_verification_failure = 1;
+ } else {
+ printk(BIOS_DEBUG,
+ "FSP_SMBIOS_MEMORY_INFO HOB: 0x%p\n",
+ memory_info_hob);
+ }
+
+#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+ if (hob_list_ptr == NULL)
+ die("ERROR - HOB pointer is NULL!\n");
+
+ /*
+ * Verify that FSP is generating the required HOBs:
+ * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
+ * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified above
+ * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified below
+ * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified above
+ * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit
+ * FSP_SMBIOS_MEMORY_INFO HOB verified above
+ */
+ if (NULL != cbmem_root) {
+ printk(BIOS_DEBUG,
+ "7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n",
+ cbmem_root);
+ data = cbmem_root->PhysicalStart;
+ printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
+ data = cbmem_root->ResourceLength;
+ printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
+ }
+ hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr);
+ if (NULL == hob_ptr.Raw) {
+ printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n");
+ fsp_verification_failure =
+ (params->pei_data->saved_data == NULL) ? 1 : 0;
+ } else {
+ printk(BIOS_DEBUG,
+ "7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n",
+ hob_ptr.Raw);
+ }
+ if (fsp_memory != NULL) {
+ printk(BIOS_DEBUG,
+ "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n",
+ fsp_memory);
+ data = fsp_memory->PhysicalStart;
+ printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
+ data = fsp_memory->ResourceLength;
+ printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
+ }
+
+ /* Verify all the HOBs are present */
+ if (fsp_verification_failure)
+ printk(BIOS_DEBUG,
+ "ERROR - Missing one or more required FSP HOBs!\n");
+
+ /* Display the HOBs */
+ print_hob_type_structure(0, hob_list_ptr);
+#endif
+
+ /* Get the address of the CBMEM region for the FSP reserved memory */
+ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
+ printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n",
+ fsp_reserved_memory_area);
+
+ /* Verify the order of CBMEM root and FSP memory */
+ if ((fsp_memory != NULL) && (cbmem_root != NULL) &&
+ (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG,
+ "ERROR - FSP reserved memory above CBMEM root!\n");
+ }
+
+ /* Verify that the FSP memory was properly reserved */
+ if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) ||
+ (fsp_memory->PhysicalStart !=
+ (unsigned int)fsp_reserved_memory_area))) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n");
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ if (cbmem_root != NULL) {
+ size_t delta_bytes = (unsigned int)smm_base
+ - cbmem_root->PhysicalStart
+ - cbmem_root->ResourceLength;
+ printk(BIOS_DEBUG,
+ "0x%08x: Chipset reserved bytes reported by FSP\n",
+ (unsigned int)delta_bytes);
+ die("Please verify the chipset reserved size\n");
+ }
+#endif
+ }
+
+ /* Verify the FSP 1.1 HOB interface */
+ if (fsp_verification_failure)
+ die("ERROR - Coreboot's requirements not met by FSP binary!\n");
+
+ /* Display the memory configuration */
+ report_memory_config();
+
+ /* Locate the memory configuration data to speed up the next reboot */
+ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr);
+ if (mrc_hob == NULL)
+ printk(BIOS_DEBUG,
+ "Memory Configuration Data Hob not present\n");
+ else if (!recovery_mode_enabled()) {
+ /* Do not save MRC data in recovery path */
+ pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob);
+ pei_ptr->data_to_save_size = ALIGN(
+ ((u32)GET_HOB_LENGTH(mrc_hob)), 16);
+ }
+}
+
+/* Initialize the UPD parameters for MemoryInit */
+__attribute__((weak)) void mainboard_memory_init_params(
+ struct romstage_params *params,
+ MEMORY_INIT_UPD *upd_ptr)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Display the UPD parameters for MemoryInit */
+__attribute__((weak)) void soc_display_memory_init_params(
+ const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new)
+{
+ printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
+ hexdump32(BIOS_SPEW, new, sizeof(*new));
+}
+
+/* Initialize the UPD parameters for MemoryInit */
+__attribute__((weak)) void soc_memory_init_params(
+ struct romstage_params *params,
+ MEMORY_INIT_UPD *upd)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/ramstage.c b/src/vendorcode/intel/fsp/fsp1_1/common/ramstage.c
new file mode 100644
index 0000000..834f148
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/ramstage.c
@@ -0,0 +1,223 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootmode.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/memmap.h>
+#include <fsp/ramstage.h>
+#include <fsp/util.h>
+#include <lib.h>
+#include <stage_cache.h>
+#include <string.h>
+#include <timestamp.h>
+
+/* SOC initialization after FSP silicon init */
+__attribute__((weak)) void soc_after_silicon_init(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Display SMM memory map */
+static void smm_memory_map(void)
+{
+ void *base;
+ size_t size;
+ int i;
+
+ printk(BIOS_SPEW, "SMM Memory Map\n");
+
+ smm_region(&base, &size);
+ printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size);
+
+ for (i = 0; i < SMM_SUBREGION_NUM; i++) {
+ if (smm_subregion(i, &base, &size))
+ continue;
+ printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size);
+ }
+}
+
+static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
+{
+ const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
+ int missing_hob = 0;
+ void *hob_list_ptr = get_hob_list();
+
+ if (!IS_ENABLED(CONFIG_DISPLAY_HOBS))
+ return;
+
+ /* Verify the HOBs */
+ if (hob_list_ptr == NULL) {
+ printk(BIOS_INFO, "ERROR - HOB pointer is NULL!\n");
+ return;
+ }
+
+ print_hob_type_structure(0, hob_list_ptr);
+
+ /*
+ * Verify that FSP is generating the required HOBs:
+ * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
+ * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit
+ * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit
+ * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit
+ * 7.5: EFI_PEI_GRAPHICS_INFO_HOB verified below,
+ * if the ImageAttribute bit is set
+ * FSP_SMBIOS_MEMORY_INFO HOB verified by raminit
+ */
+ if ((fsp_info_header->ImageAttribute & GRAPHICS_SUPPORT_BIT) &&
+ !get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) {
+ printk(BIOS_INFO, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n");
+ missing_hob = 1;
+ }
+
+ if (missing_hob)
+ printk(BIOS_INFO,
+ "ERROR - Missing one or more required FSP HOBs!\n");
+}
+
+void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
+{
+ FSP_SILICON_INIT fsp_silicon_init;
+ SILICON_INIT_UPD *original_params;
+ SILICON_INIT_UPD silicon_init_params;
+ EFI_STATUS status;
+ UPD_DATA_REGION *upd_ptr;
+ VPD_DATA_REGION *vpd_ptr;
+
+ /* Display the FSP header */
+ if (fsp_info_header == NULL) {
+ printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
+ return;
+ }
+ print_fsp_info(fsp_info_header);
+
+ /* Initialize the UPD values */
+ vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset +
+ fsp_info_header->ImageBase);
+ printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr);
+ upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
+ fsp_info_header->ImageBase);
+ printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr);
+ original_params = (void *)((u8 *)upd_ptr +
+ upd_ptr->SiliconInitUpdOffset);
+ memcpy(&silicon_init_params, original_params,
+ sizeof(silicon_init_params));
+ soc_silicon_init_params(&silicon_init_params);
+
+ /* Locate VBT and pass to FSP GOP */
+ if (IS_ENABLED(CONFIG_GOP_SUPPORT))
+ load_vbt(is_s3_wakeup, &silicon_init_params);
+ mainboard_silicon_init_params(&silicon_init_params);
+
+ /* Display the UPD data */
+ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
+ soc_display_silicon_init_params(original_params,
+ &silicon_init_params);
+
+ /* Perform silicon initialization after RAM is configured */
+ printk(BIOS_DEBUG, "Calling FspSiliconInit\n");
+ fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase
+ + fsp_info_header->FspSiliconInitEntryOffset);
+ timestamp_add_now(TS_FSP_SILICON_INIT_START);
+ printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n",
+ &silicon_init_params, fsp_silicon_init);
+ post_code(POST_FSP_SILICON_INIT);
+ status = fsp_silicon_init(&silicon_init_params);
+ timestamp_add_now(TS_FSP_SILICON_INIT_END);
+ printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
+
+ /* Mark graphics init done after SiliconInit if VBT was provided */
+#if IS_ENABLED(CONFIG_GOP_SUPPORT)
+ /* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs
+ * to be #if'd out instead of using if(). */
+ if (silicon_init_params.GraphicsConfigPtr)
+ gfx_set_init_done(1);
+#endif
+
+ display_hob_info(fsp_info_header);
+ soc_after_silicon_init();
+}
+
+static void fsp_cache_save(struct prog *fsp)
+{
+ if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP))
+ smm_memory_map();
+
+ if (prog_entry(fsp) == NULL) {
+ printk(BIOS_ERR, "ERROR: No FSP to save in cache.\n");
+ return;
+ }
+
+ stage_cache_add(STAGE_REFCODE, fsp);
+}
+
+static int fsp_find_and_relocate(struct prog *fsp)
+{
+ if (prog_locate(fsp)) {
+ printk(BIOS_ERR, "ERROR: Couldn't find %s\n", prog_name(fsp));
+ return -1;
+ }
+
+ if (fsp_relocate(fsp, prog_rdev(fsp))) {
+ printk(BIOS_ERR, "ERROR: FSP relocation failed.\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+void intel_silicon_init(void)
+{
+ struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
+ int is_s3_wakeup = acpi_is_wakeup_s3();
+
+ if (is_s3_wakeup) {
+ printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
+ stage_cache_load_stage(STAGE_REFCODE, &fsp);
+ } else {
+ fsp_find_and_relocate(&fsp);
+ printk(BIOS_DEBUG, "FSP: Saving binary in cache\n");
+ fsp_cache_save(&fsp);
+ }
+
+ /* FSP_INFO_HEADER is set as the program entry. */
+ fsp_update_fih(prog_entry(&fsp));
+
+ fsp_run_silicon_init(fsp_get_fih(), is_s3_wakeup);
+}
+
+/* Initialize the UPD parameters for SiliconInit */
+__attribute__((weak)) void mainboard_silicon_init_params(
+ SILICON_INIT_UPD *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+};
+
+/* Display the UPD parameters for SiliconInit */
+__attribute__((weak)) void soc_display_silicon_init_params(
+ const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
+{
+ printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
+ hexdump32(BIOS_SPEW, new, sizeof(*new));
+}
+
+/* Initialize the UPD parameters for SiliconInit */
+__attribute__((weak)) void soc_silicon_init_params(SILICON_INIT_UPD *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/romstage.c b/src/vendorcode/intel/fsp/fsp1_1/common/romstage.c
new file mode 100644
index 0000000..3d698bb
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/romstage.c
@@ -0,0 +1,420 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stddef.h>
+#include <arch/io.h>
+#include <arch/cbfs.h>
+#include <arch/stages.h>
+#include <arch/early_variables.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/x86/mtrr.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <elog.h>
+#include <fsp/romstage.h>
+#include <reset.h>
+#include <romstage_handoff.h>
+#include <smbios.h>
+#include <soc/intel/common/mrc_cache.h>
+#include <stage_cache.h>
+#include <timestamp.h>
+#include <tpm.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
+{
+ void *top_of_stack;
+ struct pei_data pei_data;
+ struct romstage_params params = {
+ .pei_data = &pei_data,
+ .chipset_context = fih,
+ };
+
+ post_code(0x30);
+
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ /* Load microcode before ram init */
+ if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
+ intel_update_microcode_from_cbfs();
+
+ memset(&pei_data, 0, sizeof(pei_data));
+
+ /* Display parameters */
+ printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
+ CONFIG_MMCONF_BASE_ADDRESS);
+ printk(BIOS_INFO, "Using FSP 1.1\n");
+
+ /* Display FSP banner */
+ print_fsp_info(fih);
+
+ /* Stash FSP version. */
+ params.fsp_version = fsp_version(fih);
+
+ /* Get power state */
+ params.power_state = fill_power_state();
+
+ /*
+ * Read and print board version. Done after SOC romstage
+ * in case PCH needs to be configured to talk to the EC.
+ */
+ if (IS_ENABLED(CONFIG_BOARD_ID_AUTO))
+ printk(BIOS_INFO, "MLB: board version %d\n", board_id());
+
+ /* Call into mainboard. */
+ mainboard_romstage_entry(¶ms);
+ soc_after_ram_init(¶ms);
+ post_code(0x38);
+
+ top_of_stack = setup_stack_and_mtrrs();
+
+ printk(BIOS_DEBUG, "Calling FspTempRamExit API\n");
+ timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START);
+ return top_of_stack;
+}
+
+void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
+{
+ return romstage_main(fih);
+}
+
+/* Entry from the mainboard. */
+void romstage_common(struct romstage_params *params)
+{
+ const struct mrc_saved_data *cache;
+ struct romstage_handoff *handoff;
+ struct pei_data *pei_data;
+
+ post_code(0x32);
+
+ timestamp_add_now(TS_BEFORE_INITRAM);
+
+ pei_data = params->pei_data;
+ pei_data->boot_mode = params->power_state->prev_sleep_state;
+
+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+ if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
+ boot_count_increment();
+#endif
+
+ /* Perform remaining SOC initialization */
+ soc_pre_ram_init(params);
+ post_code(0x33);
+
+ /* Check recovery and MRC cache */
+ params->pei_data->saved_data_size = 0;
+ params->pei_data->saved_data = NULL;
+ if (!params->pei_data->disable_saved_data) {
+ if (recovery_mode_enabled()) {
+ /* Recovery mode does not use MRC cache */
+ printk(BIOS_DEBUG,
+ "Recovery mode: not using MRC cache.\n");
+ } else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)
+ && (!mrc_cache_get_current_with_version(&cache,
+ params->fsp_version))) {
+ /* MRC cache found */
+ params->pei_data->saved_data_size = cache->size;
+ params->pei_data->saved_data = &cache->data[0];
+ } else if (params->pei_data->boot_mode == SLEEP_STATE_S3) {
+ /* Waking from S3 and no cache. */
+ printk(BIOS_DEBUG,
+ "No MRC cache found in S3 resume path.\n");
+ post_code(POST_RESUME_FAILURE);
+ hard_reset();
+ } else {
+ printk(BIOS_DEBUG, "No MRC cache found.\n");
+ mainboard_check_ec_image(params);
+ }
+ }
+
+ /* Initialize RAM */
+ raminit(params);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
+ /* Save MRC output */
+ if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {
+ printk(BIOS_DEBUG, "MRC data at %p %d bytes\n",
+ pei_data->data_to_save, pei_data->data_to_save_size);
+ if ((params->pei_data->boot_mode != SLEEP_STATE_S3)
+ && (params->pei_data->data_to_save_size != 0)
+ && (params->pei_data->data_to_save != NULL))
+ mrc_cache_stash_data_with_version(
+ params->pei_data->data_to_save,
+ params->pei_data->data_to_save_size,
+ params->fsp_version);
+ }
+
+ /* Save DIMM information */
+ mainboard_save_dimm_info(params);
+
+ /* Create romstage handof information */
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = (params->power_state->prev_sleep_state ==
+ SLEEP_STATE_S3);
+ else {
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
+ hard_reset();
+ }
+
+ /*
+ * Initialize the TPM, unless the TPM was already initialized
+ * in verstage and used to verify romstage.
+ */
+ if (IS_ENABLED(CONFIG_LPC_TPM) &&
+ !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&
+ !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
+ init_tpm(params->power_state->prev_sleep_state ==
+ SLEEP_STATE_S3);
+}
+
+void after_cache_as_ram_stage(void)
+{
+ /* Load the ramstage. */
+ copy_and_run();
+ die("ERROR - Failed to load ramstage!");
+}
+
+/* Initialize the power state */
+__attribute__((weak)) struct chipset_power_state *fill_power_state(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return NULL;
+}
+
+__attribute__((weak)) void mainboard_check_ec_image(
+ struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+ struct pei_data *pei_data;
+
+ pei_data = params->pei_data;
+ if (params->pei_data->boot_mode == SLEEP_STATE_S0) {
+ /* Ensure EC is running RO firmware. */
+ google_chromeec_check_ec_image(EC_IMAGE_RO);
+ }
+#endif
+}
+
+/* Board initialization before and after RAM is enabled */
+__attribute__((weak)) void mainboard_romstage_entry(
+ struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+
+ post_code(0x31);
+
+ /* Initliaze memory */
+ romstage_common(params);
+}
+
+/* Save the DIMM information for SMBIOS table 17 */
+__attribute__((weak)) void mainboard_save_dimm_info(
+ struct romstage_params *params)
+{
+ int channel;
+ CHANNEL_INFO *channel_info;
+ int dimm;
+ DIMM_INFO *dimm_info;
+ int dimm_max;
+ void *hob_list_ptr;
+ EFI_HOB_GUID_TYPE *hob_ptr;
+ int index;
+ struct memory_info *mem_info;
+ FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
+ const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
+
+ /* Locate the memory info HOB, presence validated by raminit */
+ hob_list_ptr = fsp_get_hob_list();
+ hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr);
+ memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1);
+
+ /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */
+ if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) {
+ printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n");
+ printk(BIOS_DEBUG, " 0x%02x: Revision\n",
+ memory_info_hob->Revision);
+ printk(BIOS_DEBUG, " 0x%02x: MemoryType\n",
+ memory_info_hob->MemoryType);
+ printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n",
+ memory_info_hob->MemoryFrequencyInMHz);
+ printk(BIOS_DEBUG, " %d: DataWidth in bits\n",
+ memory_info_hob->DataWidth);
+ printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n",
+ memory_info_hob->ErrorCorrectionType);
+ printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n",
+ memory_info_hob->ChannelCount);
+ for (channel = 0; channel < memory_info_hob->ChannelCount;
+ channel++) {
+ channel_info = &memory_info_hob->ChannelInfo[channel];
+ printk(BIOS_DEBUG, " Channel %d\n", channel);
+ printk(BIOS_DEBUG, " 0x%02x: ChannelId\n",
+ channel_info->ChannelId);
+ printk(BIOS_DEBUG, " 0x%02x: DimmCount\n",
+ channel_info->DimmCount);
+ for (dimm = 0; dimm < channel_info->DimmCount;
+ dimm++) {
+ dimm_info = &channel_info->DimmInfo[dimm];
+ printk(BIOS_DEBUG, " DIMM %d\n", dimm);
+ printk(BIOS_DEBUG, " 0x%02x: DimmId\n",
+ dimm_info->DimmId);
+ printk(BIOS_DEBUG, " %d: SizeInMb\n",
+ dimm_info->SizeInMb);
+ }
+ }
+ }
+
+ /*
+ * Allocate CBMEM area for DIMM information used to populate SMBIOS
+ * table 17
+ */
+ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+ printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);
+ if (mem_info == NULL)
+ return;
+ memset(mem_info, 0, sizeof(*mem_info));
+
+ /* Describe the first N DIMMs in the system */
+ index = 0;
+ dimm_max = ARRAY_SIZE(mem_info->dimm);
+ for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) {
+ if (index >= dimm_max)
+ break;
+ channel_info = &memory_info_hob->ChannelInfo[channel];
+ for (dimm = 0; dimm < channel_info->DimmCount; dimm++) {
+ if (index >= dimm_max)
+ break;
+ dimm_info = &channel_info->DimmInfo[dimm];
+
+ /* Populate the DIMM information */
+ if (dimm_info->SizeInMb) {
+ mem_info->dimm[index].dimm_size =
+ dimm_info->SizeInMb;
+ mem_info->dimm[index].ddr_type =
+ memory_info_hob->MemoryType;
+ mem_info->dimm[index].ddr_frequency =
+ memory_info_hob->MemoryFrequencyInMHz;
+ mem_info->dimm[index].channel_num =
+ channel_info->ChannelId;
+ mem_info->dimm[index].dimm_num =
+ dimm_info->DimmId;
+ switch (memory_info_hob->DataWidth) {
+ default:
+ case 8:
+ mem_info->dimm[index].bus_width =
+ MEMORY_BUS_WIDTH_8;
+ break;
+
+ case 16:
+ mem_info->dimm[index].bus_width =
+ MEMORY_BUS_WIDTH_16;
+ break;
+
+ case 32:
+ mem_info->dimm[index].bus_width =
+ MEMORY_BUS_WIDTH_32;
+ break;
+
+ case 64:
+ mem_info->dimm[index].bus_width =
+ MEMORY_BUS_WIDTH_64;
+ break;
+
+ case 128:
+ mem_info->dimm[index].bus_width =
+ MEMORY_BUS_WIDTH_128;
+ break;
+ }
+
+ /* Add any mainboard specific information */
+ mainboard_add_dimm_info(params, mem_info,
+ channel, dimm, index);
+ index++;
+ }
+ }
+ }
+ mem_info->dimm_cnt = index;
+ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+}
+
+/* Add any mainboard specific information */
+__attribute__((weak)) void mainboard_add_dimm_info(
+ struct romstage_params *params,
+ struct memory_info *mem_info,
+ int channel, int dimm, int index)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Get the memory configuration data */
+__attribute__((weak)) int mrc_cache_get_current(
+ const struct mrc_saved_data **cache)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return -1;
+}
+
+/* Save the memory configuration data */
+__attribute__((weak)) int mrc_cache_stash_data(void *data, size_t size)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return -1;
+}
+
+/* Transition RAM from off or self-refresh to active */
+__attribute__((weak)) void raminit(struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ post_code(0x34);
+ die("ERROR - No RAM initialization specified!\n");
+}
+
+void ramstage_cache_invalid(void)
+{
+ if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE))
+ /* Perform cold reset on invalid ramstage cache. */
+ hard_reset();
+}
+
+/* Display the memory configuration */
+__attribute__((weak)) void report_memory_config(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Choose top of stack and setup MTRRs */
+__attribute__((weak)) void *setup_stack_and_mtrrs(void)
+{
+ printk(BIOS_ERR, "WEAK: %s/%s called\n", __FILE__, __func__);
+ die("ERROR - Must specify top of stack!\n");
+ return NULL;
+}
+
+/* SOC initialization after RAM is enabled */
+__attribute__((weak)) void soc_after_ram_init(struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* SOC initialization before RAM is enabled */
+__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/romstage_after_verstage.S b/src/vendorcode/intel/fsp/fsp1_1/common/romstage_after_verstage.S
new file mode 100644
index 0000000..739db29
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/romstage_after_verstage.S
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
+
+.text
+.global _start
+_start:
+ /* This is the romstage entry point when CONFIG_SEPARATE_VERSTAGE
+ * is used. The stack, descriptors, and gdt are already initialized
+ * by verstage. However, in order to maintain the semantics of
+ * CAR_GLOBAL variables we need to clear those to zero. */
+ cld
+ xor %eax, %eax
+ movl $(_car_global_end), %ecx
+ movl $(_car_global_start), %edi
+ sub %edi, %ecx
+ rep stosl
+ call romstage_after_verstage
+ #include "after_raminit.S"
+
+ movb $0x69, %ah
+ jmp .Lhlt
+
+.Lhlt:
+ xchg %al, %ah
+#if IS_ENABLED(CONFIG_POST_IO)
+ outb %al, $CONFIG_POST_IO_PORT
+#else
+ post_code(POST_DEAD_CODE)
+#endif
+ movl $LHLT_DELAY, %ecx
+.Lhlt_Delay:
+ outb %al, $0xED
+ loop .Lhlt_Delay
+ jmp .Lhlt
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/stack.c b/src/vendorcode/intel/fsp/fsp1_1/common/stack.c
new file mode 100644
index 0000000..e048229
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/stack.c
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <fsp/memmap.h>
+#include <fsp/romstage.h>
+#include <fsp/stack.h>
+#include <stdlib.h>
+
+const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;
+
+/*
+ * Romstage needs quite a bit of stack for decompressing images since the lzma
+ * lib keeps its state on the stack during romstage.
+ */
+static unsigned long choose_top_of_stack(void)
+{
+ unsigned long stack_top;
+
+ /* cbmem_add() does a find() before add(). */
+ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
+ romstage_ram_stack_size);
+ stack_top += romstage_ram_stack_size;
+ return stack_top;
+}
+
+/*
+ * setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use.
+ */
+void *setup_stack_and_mtrrs(void)
+{
+ size_t alignment;
+ uint32_t aligned_ram;
+ uint32_t mtrr_mask_upper;
+ uint32_t max_mtrrs;
+ uint32_t num_mtrrs;
+ uint32_t *slot;
+ unsigned long top_of_stack;
+
+ /* Display the MTTRs */
+ soc_display_mtrrs();
+
+ /* Top of stack needs to be aligned to a 8-byte boundary. */
+ top_of_stack = choose_top_of_stack();
+ slot = (void *)top_of_stack;
+ num_mtrrs = 0;
+ max_mtrrs = soc_get_variable_mtrr_count(NULL);
+
+ /*
+ * The upper bits of the MTRR mask need to set according to the number
+ * of physical address bits.
+ */
+ mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
+ alignment = mmap_region_granularity();
+ aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size,
+ alignment);
+
+ /*
+ * The order for each MTRR is value then base with upper 32-bits of
+ * each value coming before the lower 32-bits. The reasoning for
+ * this ordering is to create a stack layout like the following:
+ *
+ * +36: MTRR mask 1 63:32
+ * +32: MTRR mask 1 31:0
+ * +28: MTRR base 1 63:32
+ * +24: MTRR base 1 31:0
+ * +20: MTRR mask 0 63:32
+ * +16: MTRR mask 0 31:0
+ * +12: MTRR base 0 63:32
+ * +8: MTRR base 0 31:0
+ * +4: Number of MTRRs to setup (described above)
+ * +0: Number of variable MTRRs to clear
+ */
+
+ /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /*
+ * +-------------------------+ Top of RAM (aligned)
+ * | System Management Mode |
+ * | code and data | Length: CONFIG_TSEG_SIZE
+ * | (TSEG) |
+ * +-------------------------+ SMM base (aligned)
+ * | |
+ * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE
+ * | |
+ * +-------------------------+ top_of_ram (aligned)
+ * | |
+ * | CBMEM Root |
+ * | |
+ * +-------------------------+
+ * | |
+ * | FSP Reserved Memory |
+ * | |
+ * +-------------------------+
+ * | |
+ * | Various CBMEM Entries |
+ * | |
+ * +-------------------------+ top_of_stack (8 byte aligned)
+ * | |
+ * | stack (CBMEM Entry) |
+ * | |
+ * +-------------------------+
+ */
+
+ /*
+ * Cache the stack and the other CBMEM entries as well as part or all
+ * of the FSP reserved memory region.
+ */
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ void *smm_base;
+ size_t smm_size;
+ uint32_t tseg_base;
+
+ /*
+ * Cache the TSEG region at the top of ram. This region is not
+ * restricted to SMM mode until SMM has been relocated. By setting
+ * the region to cacheable it provides faster access when relocating
+ * the SMM handler as well as using the TSEG region for other purposes.
+ */
+ smm_region(&smm_base, &smm_size);
+ tseg_base = (uint32_t)smm_base;
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+#endif
+
+ /* Cache the ROM as WP just below 4GiB. */
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
+ num_mtrrs++;
+
+ /* Validate the MTRR usage */
+ if (num_mtrrs > max_mtrrs) {
+ printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d",
+ max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs);
+ die("ERROR - MTRR use count incorrect!\n");
+ }
+
+ /*
+ * Save the number of MTRRs to setup and clear. Return the stack
+ * location pointing to the number of MTRRs.
+ */
+ slot = stack_push32(slot, num_mtrrs);
+ slot = stack_push32(slot, max_mtrrs);
+ return slot;
+}
+
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/stage_cache.c b/src/vendorcode/intel/fsp/fsp1_1/common/stage_cache.c
new file mode 100644
index 0000000..2d594e6
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/stage_cache.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/memmap.h>
+#include <stage_cache.h>
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+ if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
+ printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
+ *base = NULL;
+ *size = 0;
+ }
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/vbt.c b/src/vendorcode/intel/fsp/fsp1_1/common/vbt.c
new file mode 100644
index 0000000..414b88d
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/vbt.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootmode.h>
+#include <console/console.h>
+#include <fsp/ramstage.h>
+#include <fsp/util.h>
+
+/* Locate VBT and pass it to FSP GOP */
+void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
+{
+ const optionrom_vbt_t *vbt_data = NULL;
+ uint32_t vbt_len;
+
+ /* Check boot mode - for S3 resume path VBT loading is not needed */
+ if (s3_resume) {
+ printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n");
+ } else if (display_init_required()) {
+ /* Get VBT data */
+ vbt_data = fsp_get_vbt(&vbt_len);
+ if (vbt_data != NULL)
+ printk(BIOS_DEBUG, "Passing VBT to GOP\n");
+ else
+ printk(BIOS_DEBUG, "VBT not found!\n");
+ } else {
+ printk(BIOS_DEBUG, "Not passing VBT to GOP\n");
+ }
+ params->GraphicsConfigPtr = (u32)vbt_data;
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/common/verstage.c b/src/vendorcode/intel/fsp/fsp1_1/common/verstage.c
new file mode 100644
index 0000000..d7cdfdf
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/common/verstage.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/car.h>
+#include <program_loading.h>
+
+void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
+{
+ run_romstage();
+ /* Will actually never return. */
+ return NULL;
+}
diff --git a/src/vendorcode/intel/fsp/fsp2_0/common/Kconfig b/src/vendorcode/intel/fsp/fsp2_0/common/Kconfig
new file mode 100644
index 0000000..19e04f7
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/common/Kconfig
@@ -0,0 +1,6 @@
+config PLATFORM_USES_FSP2_0
+ bool
+ help
+ Include FSP 2.0 wrappers and functionality
+
+
diff --git a/src/vendorcode/intel/fsp/fsp2_0/common/Makefile.inc b/src/vendorcode/intel/fsp/fsp2_0/common/Makefile.inc
new file mode 100644
index 0000000..3e94f2f
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/common/Makefile.inc
@@ -0,0 +1,28 @@
+#
+# This file is part of the coreboot project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
+
+romstage-y += hand_off_block.c
+romstage-y += util.c
+romstage-y += memory_init.c
+
+ramstage-y += graphics.c
+ramstage-y += hand_off_block.c
+ramstage-y += notify.c
+ramstage-y += silicon_init.c
+ramstage-y += util.c
+
+CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
+
+endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/common/graphics.c b/src/vendorcode/intel/fsp/fsp2_0/common/graphics.c
new file mode 100644
index 0000000..1480179
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/common/graphics.c
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/util.h>
+
+enum pixel_format {
+ pixel_rgbx_8bpc = 0,
+ pixel_bgrx_8bpc = 1,
+ pixel_bitmask = 2, /* defined by <rgb>_mask values */
+};
+
+static const uint8_t uuid_graphics_info[16] = {
+ 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46,
+ 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07
+};
+
+struct hob_graphics_info {
+ uint64_t framebuffer_base;
+ uint32_t framebuffer_size;
+ uint32_t version;
+ uint32_t horizontal_resolution;
+ uint32_t vertical_resolution;
+ uint32_t pixel_format; /* See enum pixel_format */
+ uint32_t red_mask;
+ uint32_t green_mask;
+ uint32_t blue_mask;
+ uint32_t reserved_mask;
+ uint32_t pixels_per_scanline;
+} __attribute__((packed));
+
+struct pixel {
+ uint8_t pos;
+ uint8_t size;
+};
+
+static const struct fsp_framebuffer {
+ struct pixel red;
+ struct pixel green;
+ struct pixel blue;
+ struct pixel rsvd;
+} fsp_framebuffer_format_map[] = {
+ [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
+ [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
+};
+
+enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
+{
+ size_t size;
+ const struct hob_graphics_info *ginfo;
+ const struct fsp_framebuffer *fbinfo;
+
+ ginfo = fsp_find_extension_hob_by_uuid(uuid_graphics_info, &size);
+
+ if (!ginfo) {
+ printk(BIOS_ALERT, "Graphics hand-off block not found\n");
+ return CB_ERR;
+ }
+
+ if (ginfo->pixel_format > ARRAY_SIZE(fsp_framebuffer_format_map)) {
+ printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n",
+ ginfo->pixel_format);
+ return CB_ERR;
+ }
+
+ fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format;
+
+ framebuffer->physical_address = ginfo->framebuffer_base;
+ framebuffer->x_resolution = ginfo->horizontal_resolution;
+ framebuffer->y_resolution = ginfo->vertical_resolution;
+ framebuffer->bytes_per_line = ginfo->pixels_per_scanline * 4;
+ framebuffer->bits_per_pixel = 32;
+ framebuffer->red_mask_pos = fbinfo->red.pos;
+ framebuffer->red_mask_size = fbinfo->red.size;
+ framebuffer->green_mask_pos = fbinfo->green.pos;
+ framebuffer->green_mask_size = fbinfo->green.size;
+ framebuffer->blue_mask_pos = fbinfo->blue.pos;
+ framebuffer->blue_mask_size = fbinfo->blue.size;
+ framebuffer->reserved_mask_pos = fbinfo->rsvd.pos;
+ framebuffer->reserved_mask_size = fbinfo->rsvd.pos;
+ framebuffer->tag = LB_TAG_FRAMEBUFFER;
+ framebuffer->size = sizeof(*framebuffer);
+ return CB_SUCCESS;
+}
+
+uintptr_t fsp_load_vbt(void)
+{
+ void *vbt;
+
+ vbt = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, NULL);
+ if (!vbt)
+ printk(BIOS_NOTICE, "Could not locate a VBT file in CBFS\n");
+
+ return (uintptr_t)vbt;
+}
diff --git a/src/vendorcode/intel/fsp/fsp2_0/common/hand_off_block.c b/src/vendorcode/intel/fsp/fsp2_0/common/hand_off_block.c
new file mode 100644
index 0000000..00c5d26
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/common/hand_off_block.c
@@ -0,0 +1,305 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <commonlib/helpers.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <inttypes.h>
+#include <lib.h>
+#include <string.h>
+
+#define HOB_HEADER_LEN 8
+
+struct hob_header {
+ uint16_t type;
+ uint16_t length;
+} __attribute__((packed));
+
+struct hob_resource {
+ uint8_t owner_guid[16];
+ uint32_t type;
+ uint32_t attribute_type;
+ uint64_t addr;
+ uint64_t length;
+} __attribute__((packed));
+
+enum resource_type {
+ EFI_RESOURCE_SYSTEM_MEMORY = 0,
+ EFI_RESOURCE_MEMORY_MAPPED_IO = 1,
+ EFI_RESOURCE_IO = 2,
+ EFI_RESOURCE_FIRMWARE_DEVICE = 3,
+ EFI_RESOURCE_MEMORY_MAPPED_IO_PORT = 4,
+ EFI_RESOURCE_MEMORY_RESERVED = 5,
+ EFI_RESOURCE_IO_RESERVED = 6,
+ EFI_RESOURCE_MAX_MEMORY_TYPE = 7,
+};
+
+static const char *resource_names[] = {
+ [EFI_RESOURCE_SYSTEM_MEMORY] = "SYSTEM_MEMORY",
+ [EFI_RESOURCE_MEMORY_MAPPED_IO] = "MMIO",
+ [EFI_RESOURCE_IO] = "IO",
+ [EFI_RESOURCE_FIRMWARE_DEVICE] = "FIRMWARE_DEVICE",
+ [EFI_RESOURCE_MEMORY_MAPPED_IO_PORT] = "MMIO_PORT",
+ [EFI_RESOURCE_MEMORY_RESERVED] = "MEMORY_RESERVED",
+ [EFI_RESOURCE_IO_RESERVED] = "IO_RESERVED",
+};
+
+enum hob_type {
+ HOB_TYPE_HANDOFF = 0x0001,
+ HOB_TYPE_MEMORY_ALLOCATION = 0x0002,
+ HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003,
+ HOB_TYPE_GUID_EXTENSION = 0x0004,
+ HOB_TYPE_FV = 0x0005,
+ HOB_TYPE_CPU = 0x0006,
+ HOB_TYPE_MEMORY_POOL = 0x0007,
+ HOB_TYPE_FV2 = 0x0009,
+ HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A,
+ HOB_TYPE_UCAPSULE = 0x000B,
+ HOB_TYPE_UNUSED = 0xFFFE,
+ HOB_TYPE_END_OF_HOB_LIST = 0xFFFF,
+};
+
+/* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */
+static const uint8_t uuid_owner_bootloader_tolum[16] = {
+ 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44,
+ 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44,
+};
+
+static const uint8_t uuid_owner_fsp[16] = {
+ 0x59, 0x97, 0xa7, 0x69, 0x73, 0x13, 0x67, 0x43,
+ 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e,
+};
+
+static const uint8_t uuid_owner_tseg[16] = {
+ 0x7c, 0x74, 0x38, 0xd0, 0x0c, 0xd0, 0x80, 0x49,
+ 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55
+};
+
+static const uint8_t uuid_fsp_nv_storage[16] = {
+ 0x02, 0xcf, 0x1a, 0x72, 0x77, 0x4d, 0x2a, 0x4c,
+ 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0
+};
+
+static const uint8_t empty_uuid[16] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static const struct uuid_name_map {
+ const void *uuid;
+ const char *name;
+} uuid_names[] = {
+ { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" },
+ { uuid_owner_fsp, "FSP_RESERVED_MEMORY" },
+ { uuid_owner_tseg, "TSEG" },
+ { uuid_fsp_nv_storage, "FSP_NV_STORAGE" },
+};
+
+static const char *resource_name(enum resource_type type)
+{
+ if (type >= ARRAY_SIZE(resource_names))
+ return "UNKNOWN";
+ return resource_names[type];
+}
+
+/*
+ * Utilities for walking HOBs
+ */
+
+static bool uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16])
+{
+ return !memcmp(uuid1, uuid2, 16);
+}
+
+static const char *uuid_name(const uint8_t uuid[16])
+{
+ size_t i;
+ const struct uuid_name_map *owner_entry;
+
+ for (i = 0; i < ARRAY_SIZE(uuid_names); i++) {
+ owner_entry = uuid_names + i;
+ if (uuid_compare(uuid, owner_entry->uuid))
+ return owner_entry->name;
+ }
+ return "UNKNOWN";
+}
+
+static const struct hob_header *next_hob(const struct hob_header *parent)
+{
+ union {
+ const struct hob_header *hob;
+ uintptr_t addr;
+ } hob_walker;
+
+ hob_walker.hob = parent;
+ hob_walker.addr += parent->length;
+ return hob_walker.hob;
+}
+
+static const void *hob_header_to_struct(const struct hob_header *hob)
+{
+ union {
+ const struct hob_header *hob_hdr;
+ const void *hob_descr;
+ uintptr_t addr;
+ } hob_walker;
+
+ hob_walker.hob_hdr = hob;
+ hob_walker.addr += HOB_HEADER_LEN;
+ return hob_walker.hob_descr;
+}
+
+static const void *hob_header_to_extension_hob(const struct hob_header *hob)
+{
+ union {
+ const struct hob_header *hob_hdr;
+ const void *hob_descr;
+ uintptr_t addr;
+ } hob_walker;
+
+ hob_walker.hob_hdr = hob;
+ hob_walker.addr += HOB_HEADER_LEN + 16; /* header and 16-byte UUID */
+ return hob_walker.hob_descr;
+}
+
+static const
+struct hob_resource *hob_header_to_resource(const struct hob_header *hob)
+{
+ return hob_header_to_struct(hob);
+}
+
+/*
+ * Utilities for locating and identifying HOBs
+ */
+
+void fsp_save_hob_list(void *hob_list_ptr)
+{
+ void **cbmem_loc;
+ cbmem_loc = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*hob_list_ptr));
+ *cbmem_loc = hob_list_ptr;
+}
+
+const void *fsp_get_hob_list(void)
+{
+ void **list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME);
+
+ return (list_loc) ? (*list_loc) : NULL;
+}
+
+static const
+struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob,
+ const uint8_t uuid[16])
+{
+ const struct hob_resource *res;
+
+ for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) {
+
+ if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)
+ continue;
+
+ res = hob_header_to_resource(hob);
+ if (uuid_compare(res->owner_guid, uuid))
+ return res;
+ }
+ return NULL;
+}
+
+void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list)
+{
+ const struct hob_resource *fsp_mem;
+
+ range_entry_init(re, 0, 0, 0);
+
+ fsp_mem = find_resource_hob_by_uuid(hob_list, uuid_owner_fsp);
+
+ if (!fsp_mem) {
+ return;
+ }
+
+ range_entry_init(re, fsp_mem->addr, fsp_mem->addr + fsp_mem->length, 0);
+}
+
+/*
+ * Utilities for printing HOB information
+ */
+
+static void print_guid(const void *base)
+{
+ uint32_t big;
+ uint16_t mid[2];
+
+ const uint8_t *id = base;
+ big = read32(id + 0);
+ mid[0] = read16(id + 4);
+ mid[1] = read16(id + 6);
+
+ printk(BIOS_DEBUG, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x",
+ big, mid[0], mid[1],
+ id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]);
+}
+
+static void print_resource_descriptor(const void *base)
+{
+ const struct hob_resource *res;
+
+ res = hob_header_to_resource(base);
+
+ printk(BIOS_DEBUG, "Resource %s, attribute %x\n",
+ resource_name(res->type), res->attribute_type);
+ printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length);
+ if (!uuid_compare(res->owner_guid, empty_uuid)) {
+ printk(BIOS_DEBUG, "\tOwner GUID: ");
+ print_guid(res->owner_guid);
+ printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid));
+ }
+}
+
+
+void fsp_print_memory_resource_hobs(const void *hob_list)
+{
+ const struct hob_header *hob = hob_list;
+
+ for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) {
+ if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR)
+ print_resource_descriptor(hob);
+ }
+}
+
+const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size)
+{
+ const uint8_t *hob_uuid;
+ const struct hob_header *hob = fsp_get_hob_list();
+
+ if (!hob)
+ return NULL;
+
+ for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) {
+
+ if (hob->type != HOB_TYPE_GUID_EXTENSION)
+ continue;
+
+ hob_uuid = hob_header_to_struct(hob);
+ if (uuid_compare(hob_uuid, uuid)) {
+ *size = hob->length - (HOB_HEADER_LEN + 16);
+ return hob_header_to_extension_hob(hob);
+ }
+ }
+
+ return NULL;
+}
+
+
+const void *fsp_find_nv_storage_data(size_t *size)
+{
+ return fsp_find_extension_hob_by_uuid(uuid_fsp_nv_storage, size);
+}
diff --git a/src/vendorcode/intel/fsp/fsp2_0/common/include/fsp/api.h b/src/vendorcode/intel/fsp/fsp2_0/common/include/fsp/api.h
new file mode 100644
index 0000000..d49fc42
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/common/include/fsp/api.h
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _FSP2_0_API_H_
+#define _FSP2_0_API_H_
+
+#include <stddef.h>
+#include <memrange.h>
+#include <fsp/info_header.h>
+#include <soc/fsp/FspmUpd.h>
+#include <soc/fsp/FspsUpd.h>
+
+enum fsp_status {
+ FSP_SUCCESS = 0x00000000,
+ FSP_INVALID_PARAMETER = 0x80000002,
+ FSP_UNSUPPORTED = 0x80000003,
+ FSP_NOT_READY = 0x80000006,
+ FSP_DEVICE_ERROR = 0x80000007,
+ FSP_OUT_OF_RESOURCES = 0x80000009,
+ FSP_VOLUME_CORRUPTED = 0x8000000a,
+ FSP_NOT_FOUND = 0x8000000a,
+ FSP_TIMEOUT = 0x80000012,
+ FSP_ABORTED = 0x80000015,
+ FSP_INCOMPATIBLE_VERSION = 0x80000010,
+ FSP_SECURITY_VIOLATION = 0x8000001a,
+ FSP_CRC_ERROR = 0x8000001b,
+};
+
+enum fsp_boot_mode {
+ FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00,
+ FSP_BOOT_WITH_MINIMAL_CONFIGURATION = 0x01,
+ FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES = 0x02,
+ FSP_BOOT_ON_S4_RESUME = 0x05,
+ FSP_BOOT_ON_S3_RESUME = 0x11,
+ FSP_BOOT_ON_FLASH_UPDATE = 0x12,
+ FSP_BOOT_IN_RECOVERY_MODE = 0x20
+};
+
+enum fsp_notify_phase {
+ AFTER_PCI_ENUM = 0x20,
+ READY_TO_BOOT = 0x40
+};
+
+
+/* Main FSP stages */
+enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *r);
+enum fsp_status fsp_silicon_init(struct range_entry *r);
+enum fsp_status fsp_notify(enum fsp_notify_phase phase);
+
+/* Callbacks for updating stage-specific parameters */
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd);
+void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd);
+
+/*
+ * # DOCUMENTATION:
+ *
+ * This file defines the interface between coreboot and the FSP 2.0 wrapper
+ * fsp_memory_init(), fsp_silicon_init(), and fsp_notify() are the main entry
+ * points and map 1:1 to the FSP entry points of the same name.
+ *
+ * ### fsp_memory_init():
+ * - hob_list: retuns a pointer to the HOB storage area created by FSP
+ * - r: memory range that the binary is allowed to be loaded into
+ *
+ * This function is responsible for loading and executing the memory
+ * initialization code from the FSP-M binary. It expects this binary to reside
+ * in cbfs as FSP_M_FILE.
+ *
+ * The function takes one parameter, which is described below, but does not
+ * take in memory parameters as an argument. The memory parameters can be filled
+ * in with platform_fsp_memory_init_params_cb(). This is a callback symbol
+ * that fsp_memory_init() will call. The platform must provide this symbol.
+ *
+ * FSP returns information about the memory layout in a series of structures
+ * called hand-off-blocks (HOB). The "hob_list" output parameter will point to
+ * the start of the HOB list. The fsp reserved region will also be described by
+ * one of the HOBs. For more information on parsing these structures, see
+ * fsp/util.h
+ *
+ *
+ * ### fsp_silicon_init():
+ * - r: memory range that the binary is allowed to be loaded into
+ *
+ * This function is responsible for loading and executing the silicon
+ * initialization code from the FSP-S binary. It expects this binary to reside
+ * in cbfs as FSP_S_FILE.
+ *
+ * Like fsp_memory_init(), it provides a callback to fill in FSP-specific
+ * parameters, via platform_fsp_silicon_init_params_cb(). The platform must
+ * also provide this symbol.
+ *
+ *
+ * ### fsp_notify():
+ * - phase: Which FSP notification phase
+ *
+ * This function is responsible for loading and executing the notify code from
+ * the FSP-S binary. It expects that fsp_silicon_init() has already been called
+ * succesfully, and that the FSP-S binary is still loaded into memory.
+ */
+
+#endif /* _FSP2_0_API_H_ */
diff --git a/src/vendorcode/intel/fsp/fsp2_0/common/include/fsp/info_header.h b/src/vendorcode/intel/fsp/fsp2_0/common/include/fsp/info_header.h
new file mode 100644
index 0000000..468101e
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/common/include/fsp/info_header.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _FSP2_0_INFO_HEADER_H_
+#define _FSP2_0_INFO_HEADER_H_
+
+#include <rules.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <types.h>
+
+#define FSP_HDR_OFFSET 0x94
+#define FSP_HDR_LEN 0x48
+#define FSP_HDR_SIGNATURE "FSPH"
+#define FSP_HDR_ATTRIB_FSPT (0b0001 << 28)
+#define FSP_HDR_ATTRIB_FSPM (0b0010 << 28)
+#define FSP_HDR_ATTRIB_FSPS (0b0011 << 28)
+
+struct fsp_header {
+ uint32_t fsp_revision;
+ size_t image_size;
+ uintptr_t image_base;
+ uint32_t image_attribute;
+ size_t cfg_region_offset;
+ size_t cfg_region_size;
+ size_t notify_phase_entry_offset;
+ size_t memory_init_entry_offset;
+ size_t silicon_init_entry_offset;
+ char image_id[sizeof(uint64_t) + 1];
+ uint8_t revision;
+};
+
+enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);
+void fsp_print_header_info(const struct fsp_header *hdr);
+void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob);
+
+#if ENV_RAMSTAGE
+/*
+ * This is a FSP_INFO_HEADER that came from fsps.bin blob. It contains
+ * both SiliconInit and Notify APIs. When SiliconInit is loaded the
+ * header is saved so that when Notify is called we do not have to start
+ * header parsing again.
+ */
+extern struct fsp_header fsps_hdr;
+#endif
+
+#endif /* _FSP2_0_INFO_HEADER_H_ */
diff --git a/src/vendorcode/intel/fsp/fsp2_0/common/include/fsp/util.h b/src/vendorcode/intel/fsp/fsp2_0/common/include/fsp/util.h
new file mode 100644
index 0000000..d9d9539
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/common/include/fsp/util.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _FSP2_0_UTIL_H_
+#define _FSP2_0_UTIL_H_
+
+#include <boot/coreboot_tables.h>
+#include <fsp/info_header.h>
+#include <memrange.h>
+
+/*
+ * Hand-off-block handling functions that depend on CBMEM, and thus can only
+ * be used after cbmem_initialize().
+ */
+void fsp_save_hob_list(void *hob_list_ptr);
+const void *fsp_get_hob_list(void);
+const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size);
+const void *fsp_find_nv_storage_data(size_t *size);
+enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
+/*
+ * Hand-off-block utilities which do not depend on CBMEM, but need to be passed
+ * the HOB list explicitly.
+ */
+void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list);
+void fsp_print_memory_resource_hobs(const void *hob_list);
+
+/* Load an FSP binary into CBFS, and fill the associated fsp_header struct */
+enum cb_err fsp_load_binary(struct fsp_header *hdr, const char *name,
+ struct range_entry *r);
+/* Load a vbt.bin file for graphics. Returns 0 if a valid VBT is not found. */
+uintptr_t fsp_load_vbt(void);
+
+#endif /* _FSP2_0_UTIL_H_ */
diff --git a/src/vendorcode/intel/fsp/fsp2_0/common/memory_init.c b/src/vendorcode/intel/fsp/fsp2_0/common/memory_init.c
new file mode 100644
index 0000000..8033937
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/common/memory_init.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <memrange.h>
+#include <string.h>
+#include <timestamp.h>
+
+typedef asmlinkage enum fsp_status (*fsp_memory_init_fn)
+ (void *raminit_upd, void **hob_list);
+
+static enum fsp_status do_fsp_memory_init(void **hob_list_ptr,
+ struct fsp_header *hdr)
+{
+ enum fsp_status status;
+ fsp_memory_init_fn fsp_raminit;
+ struct FSPM_UPD fspm_upd, *upd;
+
+ post_code(0x34);
+
+ upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
+
+ if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) {
+ printk(BIOS_ERR, "Invalid FSPM signature\n");
+ return FSP_INCOMPATIBLE_VERSION;
+ }
+
+ /* Copy the default values from the UPD area */
+ memcpy(&fspm_upd, upd, sizeof(fspm_upd));
+
+ /* Give SoC and mainboard a chance to update the UPD */
+ platform_fsp_memory_init_params_cb(&fspm_upd);
+
+ /* Call FspMemoryInit */
+ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
+ printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit);
+ printk(BIOS_SPEW, "\t%p: raminit_upd\n", &fspm_upd);
+ printk(BIOS_SPEW, "\t%p: hob_list ptr\n", hob_list_ptr);
+
+ timestamp_add_now(TS_FSP_MEMORY_INIT_START);
+ status = fsp_raminit(&fspm_upd, hob_list_ptr);
+ post_code(0x37);
+ timestamp_add_now(TS_FSP_MEMORY_INIT_END);
+
+ printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
+
+ return status;
+}
+
+enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *range)
+{
+ struct fsp_header hdr;
+
+ /* TODO: do not hardcode CBFS file names */
+ if (fsp_load_binary(&hdr, "blobs/fspm.bin", range) != CB_SUCCESS)
+ return FSP_NOT_FOUND;
+
+ return do_fsp_memory_init(hob_list, &hdr);
+}
diff --git a/src/vendorcode/intel/fsp/fsp2_0/common/notify.c b/src/vendorcode/intel/fsp/fsp2_0/common/notify.c
new file mode 100644
index 0000000..820bd45
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/common/notify.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <string.h>
+
+struct fsp_notify_params {
+ enum fsp_notify_phase phase;
+};
+
+typedef asmlinkage enum fsp_status (*fsp_notify_fn)
+ (struct fsp_notify_params *);
+
+enum fsp_status fsp_notify(enum fsp_notify_phase phase)
+{
+ fsp_notify_fn fspnotify;
+ struct fsp_notify_params notify_params = { .phase = phase };
+
+ if (!fsps_hdr.silicon_init_entry_offset)
+ return FSP_NOT_FOUND;
+
+ fspnotify = (void*) (fsps_hdr.image_base +
+ fsps_hdr.notify_phase_entry_offset);
+
+ printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase);
+
+ return fspnotify(¬ify_params);
+}
diff --git a/src/vendorcode/intel/fsp/fsp2_0/common/silicon_init.c b/src/vendorcode/intel/fsp/fsp2_0/common/silicon_init.c
new file mode 100644
index 0000000..66043c8
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/common/silicon_init.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/cpu.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <string.h>
+
+struct fsp_header fsps_hdr;
+
+typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn)
+ (void *silicon_upd);
+
+static enum fsp_status do_silicon_init(struct fsp_header *hdr)
+{
+ struct FSPS_UPD upd, *supd;
+ fsp_silicon_init_fn silicon_init;
+ enum fsp_status status;
+
+ supd = (struct FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
+
+ if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) {
+ printk(BIOS_ERR, "Invalid FSPS signature\n");
+ return FSP_INCOMPATIBLE_VERSION;
+ }
+
+ memcpy(&upd, supd, sizeof(upd));
+
+ /* Give SoC/mainboard a chance to populate entries */
+ platform_fsp_silicon_init_params_cb(&upd);
+
+ silicon_init = (void *) (hdr->image_base +
+ hdr->silicon_init_entry_offset);
+
+ status = silicon_init(&upd);
+ printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
+ return status;
+}
+
+enum fsp_status fsp_silicon_init(struct range_entry *range)
+{
+ /* Load FSP-S and save FSP header. We will need it for Notify */
+ /* TODO: do not hardcode CBFS file names */
+ if (fsp_load_binary(&fsps_hdr, "blobs/fsps.bin", range) != CB_SUCCESS)
+ return FSP_NOT_FOUND;
+
+ return do_silicon_init(&fsps_hdr);
+}
diff --git a/src/vendorcode/intel/fsp/fsp2_0/common/util.c b/src/vendorcode/intel/fsp/fsp2_0/common/util.c
new file mode 100644
index 0000000..743bc9a
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/common/util.c
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <lib.h>
+#include <memrange.h>
+#include <program_loading.h>
+#include <string.h>
+
+static bool looks_like_fsp_header(const uint8_t *raw_hdr)
+{
+ if (memcmp(raw_hdr, FSP_HDR_SIGNATURE, 4)) {
+ printk(BIOS_ALERT, "Did not find a valid FSP signature\n");
+ return false;
+ }
+
+ if (read32(raw_hdr + 4) != FSP_HDR_LEN) {
+ printk(BIOS_ALERT, "FSP header has invalid length\n");
+ return false;
+ }
+
+ return true;
+}
+
+enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob)
+{
+ const uint8_t *raw_hdr = fsp_blob;
+
+ if (!looks_like_fsp_header(raw_hdr))
+ return CB_ERR;
+
+ hdr->revision = read8(raw_hdr + 11);
+ hdr->fsp_revision = read32(raw_hdr + 12);
+ memcpy(hdr->image_id, raw_hdr + 16, ARRAY_SIZE(hdr->image_id));
+ hdr->image_id[ARRAY_SIZE(hdr->image_id) - 1] = '\0';
+ hdr->image_size = read32(raw_hdr + 24);
+ hdr->image_base = read32(raw_hdr + 28);
+ hdr->image_attribute = read32(raw_hdr + 32);
+ hdr->cfg_region_offset = read32(raw_hdr + 36);
+ hdr->cfg_region_size = read32(raw_hdr + 40);
+ hdr->notify_phase_entry_offset = read32(raw_hdr + 56);
+ hdr->memory_init_entry_offset = read32(raw_hdr + 60);
+ hdr->silicon_init_entry_offset = read32(raw_hdr + 68);
+
+ return CB_SUCCESS;
+}
+
+void fsp_print_header_info(const struct fsp_header *hdr)
+{
+ printk(BIOS_DEBUG, "Revision %u, image ID: %s, base 0x%lx + 0x%zx\n",
+ hdr->revision, hdr->image_id, hdr->image_base, hdr->image_size);
+ printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n",
+ hdr->cfg_region_offset, hdr->cfg_region_size);
+
+ if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPM) {
+ printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n",
+ hdr->memory_init_entry_offset);
+ }
+
+ if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPS) {
+ printk(BIOS_DEBUG, "\tSilicon init offset 0x%zx\n",
+ hdr->silicon_init_entry_offset);
+ printk(BIOS_DEBUG, "\tNotify phase offset 0x%zx\n",
+ hdr->notify_phase_entry_offset);
+ }
+
+}
+
+/* TODO: this won't work for SoC's that need to XIP certain modules. */
+enum cb_err fsp_load_binary(struct fsp_header *hdr,
+ const char *name,
+ struct range_entry *range)
+{
+ struct cbfsf file_desc;
+ struct region_device file_data;
+ void *membase;
+
+ if (cbfs_boot_locate(&file_desc, name, NULL)) {
+ printk(BIOS_ERR, "Could not locate %s in CBFS\n", name);
+ return CB_ERR;
+ }
+
+ cbfs_file_data(&file_data, &file_desc);
+
+ /* Map just enough of the file to be able to parse the header. */
+ membase = rdev_mmap(&file_data, FSP_HDR_OFFSET, FSP_HDR_LEN);
+
+ if (membase == NULL) {
+ printk(BIOS_ERR, "Could not mmap() '%s' FSP header.\n", name);
+ return CB_ERR;
+ }
+
+ if (fsp_identify(hdr, membase) != CB_SUCCESS) {
+ rdev_munmap(&file_data, membase);
+ printk(BIOS_ERR, "%s did not have a valid FSP header\n", name);
+ return CB_ERR;
+ }
+
+ rdev_munmap(&file_data, membase);
+
+ fsp_print_header_info(hdr);
+
+ /* Check if size specified in the header matches the cbfs file size */
+ if (region_device_sz(&file_data) < hdr->image_size) {
+ printk(BIOS_ERR, "%s size bigger than cbfs file.\n", name);
+ return CB_ERR;
+ }
+
+ /* Check if the binary load address is within expected range */
+ /* TODO: this doesn't check the current running program footprint. */
+ if (range_entry_base(range) > hdr->image_base ||
+ range_entry_end(range) <= hdr->image_base + hdr->image_size) {
+ printk(BIOS_ERR, "%s is outside of allowed range\n", name);
+ return CB_ERR;
+ }
+
+ /* Load binary into memory. */
+ if (rdev_readat(&file_data, (void *)hdr->image_base, 0, hdr->image_size) < 0)
+ return CB_ERR;
+
+ /* Signal that FSP component has been loaded. */
+ prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL);
+
+ return CB_SUCCESS;
+}
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