[coreboot-gerrit] New patch to review for coreboot: lib/regscript: Add exclusive-or (xor) support
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Sun Apr 24 15:39:26 CEST 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14495
-gerrit
commit 4c50f9d55689e9154edc727794c15714c674021f
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sat Apr 23 07:58:27 2016 -0700
lib/regscript: Add exclusive-or (xor) support
Add xor support which enables toggling of a bit:
* REG_SCRIPT_COMMAND_RXW enum value
* REG_*_RXW* macros to support using REG_SCRIPT_COMMAND_RXW
* REG_*_XOR* macros to support using REG_SCRIPT_COMMAND_RXW
* reg_script_rxw routine to perform and/xor operation
* case in reg_script_run_step to call reg_script_rxw
TEST=Build and run on Galileo Gen2
Change-Id: I50a492c7c2643df5dc2d2fa7113e3722c1e480c7
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/include/reg_script.h | 57 ++++++++++++++++++++++++++++++++++++++++++++++++
src/lib/reg_script.c | 38 ++++++++++++++++++++++++++++++++
2 files changed, 95 insertions(+)
diff --git a/src/include/reg_script.h b/src/include/reg_script.h
index 60b1188..741641a 100644
--- a/src/include/reg_script.h
+++ b/src/include/reg_script.h
@@ -43,6 +43,7 @@ enum {
REG_SCRIPT_COMMAND_READ,
REG_SCRIPT_COMMAND_WRITE,
REG_SCRIPT_COMMAND_RMW,
+ REG_SCRIPT_COMMAND_RXW,
REG_SCRIPT_COMMAND_POLL,
REG_SCRIPT_COMMAND_SET_DEV,
REG_SCRIPT_COMMAND_NEXT,
@@ -156,6 +157,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0)
#define REG_PCI_RMW32(reg_, mask_, value_) \
REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0)
+#define REG_PCI_RXW8(reg_, mask_, value_) \
+ REG_SCRIPT_PCI(RXW, 8, reg_, mask_, value_, 0)
+#define REG_PCI_RXW16(reg_, mask_, value_) \
+ REG_SCRIPT_PCI(RXW, 16, reg_, mask_, value_, 0)
+#define REG_PCI_RXW32(reg_, mask_, value_) \
+ REG_SCRIPT_PCI(RXW, 32, reg_, mask_, value_, 0)
#define REG_PCI_OR8(reg_, value_) \
REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0)
#define REG_PCI_OR16(reg_, value_) \
@@ -168,6 +175,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_)
#define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \
REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_)
+#define REG_PCI_XOR8(reg_, value_) \
+ REG_SCRIPT_PCI(RXW, 8, reg_, 0xff, value_, 0)
+#define REG_PCI_XOR16(reg_, value_) \
+ REG_SCRIPT_PCI(RXW, 16, reg_, 0xffff, value_, 0)
+#define REG_PCI_XOR32(reg_, value_) \
+ REG_SCRIPT_PCI(RXW, 32, reg_, 0xffffffff, value_, 0)
/*
* Legacy IO
@@ -196,6 +209,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0)
#define REG_IO_RMW32(reg_, mask_, value_) \
REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0)
+#define REG_IO_RXW8(reg_, mask_, value_) \
+ REG_SCRIPT_IO(RXW, 8, reg_, mask_, value_, 0)
+#define REG_IO_RXW16(reg_, mask_, value_) \
+ REG_SCRIPT_IO(RXW, 16, reg_, mask_, value_, 0)
+#define REG_IO_RXW32(reg_, mask_, value_) \
+ REG_SCRIPT_IO(RXW, 32, reg_, mask_, value_, 0)
#define REG_IO_OR8(reg_, value_) \
REG_IO_RMW8(reg_, 0xff, value_)
#define REG_IO_OR16(reg_, value_) \
@@ -208,6 +227,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_)
#define REG_IO_POLL32(reg_, mask_, value_, timeout_) \
REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_)
+#define REG_IO_XOR8(reg_, value_) \
+ REG_IO_RXW8(reg_, 0xff, value_)
+#define REG_IO_XOR16(reg_, value_) \
+ REG_IO_RXW16(reg_, 0xffff, value_)
+#define REG_IO_XOR32(reg_, value_) \
+ REG_IO_RXW32(reg_, 0xffffffff, value_)
/*
* Memory Mapped IO
@@ -236,6 +261,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0)
#define REG_MMIO_RMW32(reg_, mask_, value_) \
REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0)
+#define REG_MMIO_RXW8(reg_, mask_, value_) \
+ REG_SCRIPT_MMIO(RXW, 8, reg_, mask_, value_, 0)
+#define REG_MMIO_RXW16(reg_, mask_, value_) \
+ REG_SCRIPT_MMIO(RXW, 16, reg_, mask_, value_, 0)
+#define REG_MMIO_RXW32(reg_, mask_, value_) \
+ REG_SCRIPT_MMIO(RXW, 32, reg_, mask_, value_, 0)
#define REG_MMIO_OR8(reg_, value_) \
REG_MMIO_RMW8(reg_, 0xff, value_)
#define REG_MMIO_OR16(reg_, value_) \
@@ -248,6 +279,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_)
#define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \
REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_)
+#define REG_MMIO_XOR8(reg_, value_) \
+ REG_MMIO_RXW8(reg_, 0xff, value_)
+#define REG_MMIO_XOR16(reg_, value_) \
+ REG_MMIO_RXW16(reg_, 0xffff, value_)
+#define REG_MMIO_XOR32(reg_, value_) \
+ REG_MMIO_RXW32(reg_, 0xffffffff, value_)
/*
* Access through a device's resource such as a Base Address Register (BAR)
@@ -276,6 +313,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0)
#define REG_RES_RMW32(bar_, reg_, mask_, value_) \
REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0)
+#define REG_RES_RXW8(bar_, reg_, mask_, value_) \
+ REG_SCRIPT_RES(RXW, 8, bar_, reg_, mask_, value_, 0)
+#define REG_RES_RXW16(bar_, reg_, mask_, value_) \
+ REG_SCRIPT_RES(RXW, 16, bar_, reg_, mask_, value_, 0)
+#define REG_RES_RXW32(bar_, reg_, mask_, value_) \
+ REG_SCRIPT_RES(RXW, 32, bar_, reg_, mask_, value_, 0)
#define REG_RES_OR8(bar_, reg_, value_) \
REG_RES_RMW8(bar_, reg_, 0xff, value_)
#define REG_RES_OR16(bar_, reg_, value_) \
@@ -288,6 +331,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_)
#define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \
REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_)
+#define REG_RES_XOR8(bar_, reg_, value_) \
+ REG_RES_RXW8(bar_, reg_, 0xff, value_)
+#define REG_RES_XOR16(bar_, reg_, value_) \
+ REG_RES_RXW16(bar_, reg_, 0xffff, value_)
+#define REG_RES_XOR32(bar_, reg_, value_) \
+ REG_RES_RXW32(bar_, reg_, 0xffffffff, value_)
#if IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \
@@ -307,10 +356,14 @@ IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL)
REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0)
#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \
REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0)
+#define REG_IOSF_RXW(unit_, reg_, mask_, value_) \
+ REG_SCRIPT_IOSF(RXW, unit_, reg_, mask_, value_, 0)
#define REG_IOSF_OR(unit_, reg_, value_) \
REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
+#define REG_IOSF_XOR(unit_, reg_, value_) \
+ REG_IOSF_RXW(unit_, reg_, 0xffffffff, value_)
#endif /* CONFIG_SOC_INTEL_BAYTRAIL || CONFIG_SOC_INTEL_FSP_BAYTRAIL*/
/*
@@ -328,10 +381,14 @@ IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL)
REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0)
#define REG_MSR_RMW(reg_, mask_, value_) \
REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0)
+#define REG_MSR_RXW(reg_, mask_, value_) \
+ REG_SCRIPT_MSR(RXW, reg_, mask_, value_, 0)
#define REG_MSR_OR(reg_, value_) \
REG_MSR_RMW(reg_, -1ULL, value_)
#define REG_MSR_POLL(reg_, mask_, value_, timeout_) \
REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_)
+#define REG_MSR_XOR(reg_, value_) \
+ REG_MSR_RXW(reg_, -1ULL, value_)
/*
* Chain to another table.
diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c
index 7f82000..02b516d 100644
--- a/src/lib/reg_script.c
+++ b/src/lib/reg_script.c
@@ -521,6 +521,41 @@ static void reg_script_rmw(struct reg_script_context *ctx)
reg_script_set_step(ctx, step);
}
+static void reg_script_rxw(struct reg_script_context *ctx)
+{
+ uint64_t value;
+ const struct reg_script *step = reg_script_get_step(ctx);
+ struct reg_script write_step = *step;
+
+/*
+ * XOR logic table
+ * Input XOR Value
+ * 0 0 0
+ * 0 1 1
+ * 1 0 1
+ * 1 1 1
+ *
+ * Supported operations
+ *
+ * Input Mask Temp XOR Value Operation
+ * 0 0 0 0 0 Clear bit
+ * 1 0 0 0 0
+ * 0 0 0 1 1 Set bit
+ * 1 0 0 1 1
+ * 0 1 0 0 0 Preserve bit
+ * 1 1 1 0 1
+ * 0 1 0 1 1 Toggle bit
+ * 1 1 1 1 0
+ */
+ value = reg_script_read(ctx);
+ value &= step->mask;
+ value ^= step->value;
+ write_step.value = value;
+ reg_script_set_step(ctx, &write_step);
+ reg_script_write(ctx);
+ reg_script_set_step(ctx, step);
+}
+
/* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT
* as recursive call with a new context that has the same dev and resource
* as the previous one. That will run to completion and then move on to the
@@ -544,6 +579,9 @@ static void reg_script_run_step(struct reg_script_context *ctx,
case REG_SCRIPT_COMMAND_RMW:
reg_script_rmw(ctx);
break;
+ case REG_SCRIPT_COMMAND_RXW:
+ reg_script_rxw(ctx);
+ break;
case REG_SCRIPT_COMMAND_POLL:
for (try = 0; try < step->timeout; try += POLL_DELAY) {
value = reg_script_read(ctx) & step->mask;
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